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S1D13742 mobile graphics engine hardware functional specification document number: x63a-a-001-06 status: revision 6.01 - epson confidential issue date: 2007/09/18 ? seiko epson corporation 2004 - 2007. all rights reserved. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. the programs/technologies descri bed in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners www.datasheet.co.kr datasheet pdf - http://www..net/
page 2 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 3 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 overview description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 integrated frame buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 input data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 display support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 display features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.1 intel 80 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.2 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.3 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.4 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.5 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4.3 summary of configuration options . . . . . . . . . . . . . . . . . . . . . . 18 5 pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 intel 80 data pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 lcd interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 lcd interface data pins . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 d.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . 22 6.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 a.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.1 input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.2 pll clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 reset# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 host interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 www.datasheet.co.kr datasheet pdf - http://www..net/
page 4 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.3.1 intel 80 interface timing - 1.8 volt . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3.2 intel 80 interface timing - 3.3 volt . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3.3 definition of transition time to hi-z state . . . . . . . . . . . . . . . . . . . . . . 34 7.4 display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 7.4.1 tft power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.2 tft power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4.3 18/36-bit tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.1 clock descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.2 pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.3 clocks versus functions . . . . . . . . . . . . . . . . . . . . . . . . . . .42 8.4 setting sysclk and pclk . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.2 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 9.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 9.3.1 read-only configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3.2 clock configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3.3 panel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3.4 input mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3.5 display mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 9.3.6 window settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.3.7 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3.8 gamma correction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.9 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 9.3.10 general purpose io pins registers . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10 frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11 intel 80, 8-bit interface color formats . . . . . . . . . . . . . . . . . . . . . . . . .75 11.1 16 bpp mode (r 5-bit, g 6-bit, b 5-bit), 65,536 colors . . . . . . . . . . . . . . .75 11.2 18 bpp (r 6-bit, g 6-bit, b 6-bit), 262,144 colors . . . . . . . . . . . . . . . . .76 11.3 24 bpp (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . .77 12 intel 80, 16-bit interface color formats . . . . . . . . . . . . . . . . . . . . . . . . .78 12.1 16 bpp (r 5-bit, g 6-bit, b 5-bit), 65,536 colors . . . . . . . . . . . . . . . . . .78 12.2 18 bpp mode 1 (r 6-bit, g 6-bit, b 6-bit), 262,144 colors . . . . . . . . . . . . . .79 12.3 18 bpp mode 2 (r 6-bit, g 6-bit, b 6-bit), 262,144 colors . . . . . . . . . . . . . .80 12.4 24 bpp mode 1 (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors . . . . . . . . . . . .81 12.5 24 bpp mode 2 (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors . . . . . . . . . . . .82 13 yuv timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 13.1 yuv 4:2:2 with intel 80, 8-bit interface . . . . . . . . . . . . . . . . . . . . . 84 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 5 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 13.2 yuv 4:2:0 odd line with intel 80, 8-bit interface . . . . . . . . . . . . . . . . 84 13.3 yuv 4:2:0 even line with intel 80, 8-bit interface . . . . . . . . . . . . . . . 85 13.4 yuv 4:2:2 with intel 80, 16-bit interface . . . . . . . . . . . . . . . . . . . . 8 6 13.5 yuv 4:2:0 odd line with intel 80, 16-bit interface . . . . . . . . . . . . . . . 87 13.6 yuv 4:2:0 even line with intel 80, 16-bit interface . . . . . . . . . . . . . . . 88 14 gamma correction look-up table architecture . . . . . . . . . . . . . . . . . . . 89 14.1 gamma correction example programming . . . . . . . . . . . . . . . . . . . 90 15 display data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 16 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.1 concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.2 90 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.2.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 16.3 180 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16.3.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 16.4 270 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16.4.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 17 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1 using the intel 80 interface . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1.1 register write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.1.2 register read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.1.3 new window aperture write procedure . . . . . . . . . . . . . . . . . . . . . . . 100 17.1.4 opening multiple windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 17.1.5 individual memory location reads . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18 double buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.1 double buffer controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19 interfacing the S1D13742 and a tft panel . . . . . . . . . . . . . . . . . . . . . . 106 19.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 19.1.1 electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 19.1.2 S1D13742 register settings for 352x416 tft panel . . . . . . . . . . . . . . . . . 107 19.1.3 S1D13742 register settings for 800x480 tft panel . . . . . . . . . . . . . . . . . 109 19.2 host bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 19.2.1 host bus timing for 352x416 tft panel . . . . . . . . . . . . . . . . . . . . . . . 112 19.2.2 host bus timing for 800x480 tft panel . . . . . . . . . . . . . . . . . . . . . . . 113 19.3 panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 19.3.1 panel timing for 352x416 panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.3.2 panel timing for 800x480 panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 19.4 example play.exe scripts . . . . . . . . . . . . . . . . . . . . . . . . . . 116 19.5 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 19.5.1 documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 www.datasheet.co.kr datasheet pdf - http://www..net/
page 6 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 20 pll power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 123 20.1 guidelines for pll power layout . . . . . . . . . . . . . . . . . . . . . . 12 3 21 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 22 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23 sales and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 23.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 7 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 1 introduction 1.1 scope this is the hardware functional specification for the S1D13742 embedded memory lcd controller. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences: video subsystem designers and software developers. this document is updated as appropriate. please check the epson research and devel- opment website at www.erd.epson.com for the latest revision of this document before beginning any development. we appreciate your comments on our documentation. please contact us via email at documentation@erd.epson.com. 1.2 overview description the S1D13742 is a color lcd graphics controller with an embedded 768k byte display buffer. the S1D13742 supports a 8/16-bit intel 80 cpu architecture while providing high performance bandwidth into display memory allowing for fast screen updates. products requiring a rotated display image can take advantage of the swivelview? feature which provides hardware rotation of the display memory transparent to the software appli- cation. resolutions supported include 800x480 single buffered and 352x416 double buffered. the S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. www.datasheet.co.kr datasheet pdf - http://www..net/
page 8 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 2 features 2.1 integrated frame buffer ? embedded 768k byte sram display buffer. 2.2 cpu interface ? 8/16-bit intel 80 interface (used for display or register data). ? chip select is used to select device. when inactive, any input data/command will be ignored. 2.3 input data formats ? rgb: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). ? yuv 4:2:2, 4:2:0 (internal yuv to rgb converter stored as 16 or 18 bpp). note all input data must be internally converted to the same format before being stored in the display buffer. different data types can not be mixed within a common display buffer. 2.4 display support ? active matrix tft interface. ? 18/36-bit interface. ? supports resolutions up to 800x480. 2.5 display modes ? 16/18 bit-per-pixel (bpp) color depths. ? 16 bpp to 18 bpp conversion: input data can be converted from 16 bpp to 18 bpp in one of three ways. 1. rgb (5:6:5) msb copying to create new lsb for the red and blue components. this conversion is done prior to storing in memory, as this allows for 16 bpp and 18 bpp input data to be mixed. 2. gamma correction look-up-tables: there are three, 64 position, 8-bit wide lut?s. the data stored in memory can be used as an index into these tables. the lut?s are placed on the display side and therefore do not affect the data stored in memory. 3. rgb (5:6:5) stored in memory: lut is by-passed. copy msb to lsb for red and blue during the display read from memory. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 9 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 2.6 display features ? all display writes will be handled by window apertures/position for complete or partial display updates. all window coordinates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place). ? swivelview?: 90, 180, 270 counter-clockwise hardware rotation of display image. all displayed windows can have independent rotation. no additional programming necessary when enabling these modes. ? double-buffer available to prevent image tearing during streaming input. resolutions supported must fit inside 384k bytes (? of total available display buffer). typical reso- lution of 352x416. ? pixel doubling: horizontal and vertical averaging for smooth doubling of a single window. ? pixel halving: no limitation on number of windows. 2.7 clock source ? internal programmable pll. ? single mhz clock input: clki. ? clki available as clkout (separate clkouten pin associated with output). ? output state = 0 when disabled. 2.8 miscellaneous ? hardware / software power save mode. ? input pin to enable/disable power save mode. ? general purpose input/output pins are available (gpio[7:0]). ? int pin associated with selectable gpio inputs. ? package: fcbga 121-pin package qfp20 144-pin package www.datasheet.co.kr datasheet pdf - http://www..net/
page 10 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 3 block diagram figure 3-1: block diagram lcd disp pipe intel 80 8/16 if yuv converter yuv to rgb gamma correction memory controller lcd if lcd ctc registers clocks test mux pclk pclk pclk mclk mclk mclk double mclk mclk mclk regwrclk buffer controller rotation (pixel halving) mclk pclk data control www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 11 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 4 pinout diagram 4.1 pin-out figure 4-1: S1D13742 fcbga pinout (top view) a nc nc clkout clki md3 md4 md5 md6 md7 nc nc b nc md2 md12 clkouten md13 md14 md15 md8 md9 md10 nc c md0 md11 md1 iovdd vss vss cs# we# rd# d/c# de d reset# te gpio_int pllvdd vcp pllvss corevdd iovdd hs vs pclk e test1 test2 testen corevdd vss vss vss piovdd nc vd35 vd34 f test0 scanen cnf0 vss vss vss vss vd33 vd32 vd31 vd30 g gpio0 gpio1 cnf1 piovdd vss vss corevdd vd29 vd28 vd27 vd26 h gpio2 gpio3 cnf2 iovdd piovdd corevdd piovdd vd25 vd24 vd23 vd22 j gpio4 gpio5 pwrsve vd21 vd20 vd19 vd18 vd17 vd16 vd15 vd14 k nc gpio6 gpio7 vd13 vd12 vd11 vd10 vd9 vd8 vd7 nc l nc nc vd6 vd5 vd4 vd3 vd2 vd1 vd0 nc nc 1234567891011 www.datasheet.co.kr datasheet pdf - http://www..net/
page 12 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential figure 4-2: S1D13742 qfp20 pinout (top view) index piovdd vss corevdd vss de hs vs pclk vd34 vd35 vd33 vd32 vd31 piovdd vss vd30 piovdd vss vd26 vd27 vd28 vd29 vd24 vd23 vd22 vd15 vd14 corevdd vss piovdd piovdd gpio7 vss piovdd vss corevdd vd6 vd5 vd13 vd21 vd4 vd12 vd20 vd3 vd11 vd19 piovdd vd2 vss piovdd vd10 vss vd18 vd1 vd9 vd17 vd25 vd0 vd8 vd16 vd7 vss corevdd vss vss 73 72 37 36 1 144 109 108 vss corevdd vss iovdd md0 md11 gpio_int te reset# testen scanen test2 test1 test0 cnf0 vss corevdd gpio0 gpio1 cnf1 cnf2 gpio3 gpio2 gpio4 gpio5 pwrsve gpio6 vss iovdd md2 md1 md12 vss iovdd clkout clkouten vss corevdd clki vss iovdd pllvdd vcp pllvss md13 md3 md4 md14 iovdd vss cs# md15 md5 md6 corevdd vss md8 we# rd# md9 md7 md10 d/c# iovdd vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc 123456789101112131415161718192021222324252627282930313233343536 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 13 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 4.2 pin descriptions key: 1 h system is iovdd and piovdd (see section 6, ?d.c. characteristics?). 2 l system is corevdd (see section 6, ?d.c. characteristics?). 3 lvcmos is low voltage cmos (see section 6, ?d.c. characteristics?). pin types i = input o=output io = bi-directional (input/output) p=power pin reset# / power save status h = high level output l = low level output hi-z = high impedance table 4-1: cell description item description hi h system 1 lvcmos 3 input buffer his h system lvcmos schmitt input buffer hid h system lvcmos input buffer with pull-down resistor ho h system lvcomos output buffer hb h system lvcmos bidirectional buffer hbd h system lvcmos bidirectional buffer with pull-down resistor hb_dsel h system lvcmos bidirectional buffer with drive selector lids l system 2 lvcmos schmitt input buffer with pull-down resistor litr l system transparent input buffer www.datasheet.co.kr datasheet pdf - http://www..net/
page 14 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 4.2.1 intel 80 host interface table 4-2: host interface pin descriptions pin name type fcbga pin # qfp pin # cell io voltage reset# state power save status description md[15:0] io b7,b6, b5,b3, c2,b10, b9, b8, a9,a8,a7, a6,a5,b2, c3,c1 131,127, 124,111, 100,141, 139,136, 140,133, 132,126, 125,109, 110,101 hb iovdd hi-z hi-z intel 80 data lines. ? for the S1D13742b00, when the 8-bit bus interface is selected by cnf1, md[15:8] are pulled low by internal resistors. ? for the S1D13742b01, when the 8-bit bus interface is selected by cnf1, md[15:8] should be connected to vss. note: the host data lines can be swapped (i.e. md15 = md0) using the cnf0 pin. for details, see section 4.3, ?summary of configuration options? on page 18. we# i c8 137 hi iovdd input input this input pin is the write enable signal. rd# i c9 138 hi iovdd input input this input pin is the read enable signal. cs# i c7 130 hi iovdd input input this input pin is the chip select signal. d/c# i c10 142 hi iovdd input input this input pin is used to select between intel 80 address and data te o d2 98 ho iovdd l l tearing effect: this pin will reflect the vsync, hsync or the or?d combination status of the display. gpio_int o d3 99 ho iovdd l output this interrupt pin is associated with selected gpio pins when configured as inputs or outputs. interrupt functionality is not affected by power save. see section 9.3.10, ?general purpose io pins registers? on page 72 for operational description. reset# i d1 97 hi iovdd input input active low input to set all internal registers to the default state and to force all signals to their inactive states. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 15 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 4.2.2 lcd interface note the lcd interface requires a separate power rail (piovdd) to support the configurable io drive. for details, see the cnf2 description in section 4.3, ?summary of configura- tion options? on page 18. note input of vd[35:0] is used for production test only. table 4-3: lcd interface pin descriptions pin name type fcbga pin # qfp pin # cell io voltage reset# state power save status description vd[35:0] io e10,e11, f8,f9,f10, f11,g8, g9,g10, g11,h8, h9,h10, h11,j4,j5, j6,j7,j8,j9, j10,j11,k4, k5,k6, k7, k8,k9,k10, l3,l4,l5,l6, l7,l8,l9 13,12,14,15, 16,19,25,24, 23,22,46,26, 27,28,63,60, 57,50,47,43, 29,30,64,61, 58,51,48,44, 42,66,65,62, 59,54,49,45 hb_ dsel piovdd l l panel data bits 35-0. vd[35:0] are used for all modes. in 2 pixels/clock mode, vd[17:0] represent the 1st pixel sent in a 2 pixel/clock operation. note: the panel data lines can be swapped (i.e. vd23 = vd0) using the vd data swap bit, reg[14h] bit 7. note: the vd output drive is selectable between 2.5ma and 6.5ma using the cnf2 pin. for details, see section 4.3, ?summary of configuration options? on page 18. vs o d10 10 ho piovdd h l this output pin is the vertical sync pulse hs o d9 9 ho piovdd h l this output is the horizontal sync pulse pclk o d11 11 ho piovdd clki l this output pin is the data clock de o c11 8 ho piovdd l l this output pin is the data enable www.datasheet.co.kr datasheet pdf - http://www..net/
page 16 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 4.2.3 clocks 4.2.4 miscellaneous table 4-4: clock input pin descriptions pin name type fcbga pin # qfp pin # cell io voltage reset# state power save status description clki i a4 118 his iovdd input input mhz input for pll operation or mhz input if pll is bypassed input frequency range: 1mhz ~ 33mhz clkout o a3 114 ho iovdd l clki this output pin represents the clki pin if enabled by clkouten. when disabled the output is low. note: this output is not affected by the various power save modes clkouten i b4 115 hi iovdd input input this pin enables/disables the clkout pin. table 4-5: miscellaneous pin descriptions pin name type fcbga pin # qfp pin # cell io voltage reset# state power save status description cnf[2:0] i h3,g3,f 3 85,86,91 hi iovdd input input these inputs are used for power-up configuration. for details, see section 4.3, ?summary of configuration options? on page 18. note: these pins must be connected directly to iovdd or vss. testen i e3 96 lids iovdd ? ? test enable input used for production test only this pin should be left unconnected for normal use. gpio[7:0] io k3,k2, j2,j1, h2,h1,g 2, g1 71,79,81, 82,84,83, 87,88 hbd iovdd l pull down active these pins are general purpose input/output pins. these pins have internal pull-down resistors which can be controlled using reg[64h]. pwrsve i j3 80 hi iovdd input input this pin enables/disables the standby power save mode when unused this pin must be connected to vss. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 17 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 4.2.5 power and ground test[2:0] i e2,e1,f1 94,93,92 hid iovdd ? ? these are test function pins and are used for production test only. these pins should be left unconnected for normal operation. scanen i f2 95 hid iovdd ? ? this is the test scan enable input and is used for production test only. this pin should be left unconnected for normal operation. vcp i d5 122 litr pllvdd ? ? this is the pll vcp test pin and is used for production test only. this pin should be left unconnected for normal operation. nc ? a1,a2, a10,a11, b1,b11, e9,k1,k 11,l1,l2, l10,l11 1,2,3, 35,36, 37,72, 73,74, 75,76, 106,107, 108 ? ? ? ? these pins are not connected. table 4-6: power and ground pin descriptions pin name type fcbga pin # qfp pin # cell description corevdd p d7,e4,g7,h6 6,31,40,67,89, 104,117,134 p core power supply iovdd p c4,d8,h4 77,102,113, 120,128,143 p io power supply for the host interface piovdd p e8,g4,h5,h7 4,17,20,33,38, 52,55,69 p io power supply for the panel interface pllvdd p d4 121 p pll power supply pllvss p d6 123 p gnd for pll vss p c5,c6,e5,e6, e7,f4, f5,f6, f7,g5,g6 5,7,18,21,32, 34,39,41,53, 56,68,70,78, 90,103,105, 112,116,119, 129, 135,144 pgnd table 4-5: miscellaneous pin descriptions (continued) pin name type fcbga pin # qfp pin # cell io voltage reset# state power save status description www.datasheet.co.kr datasheet pdf - http://www..net/
page 18 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 4.3 summary of configuration options these pins are used for power-up configuration and must be connected directly to iovdd or vss. the state of cnf[2:0] may be changed at any time. note when cnf1=0, all register access is 8-bit only. when cnf1 =1 (16-bit): all register access is 8-bit only (the most significant byte on the data bus is ignored) except the memory data port. access to the mem- ory data port is 16-bit. table 4-7: summary of power-on/reset options configuration input power-on/reset state 1 (connected to iovdd) 0 (connected to vss) cnf0 host data lines are normal: if cnf1 = 1, then d15 = d15, etc. if cnf1 = 0, then d7 = d7, etc. host data lines are swapped: if cnf1 = 1, then d15 = d0, etc. if cnf1 = 0, then d7 = d0, etc. cnf1 host data is 16-bit host data is 8-bit cnf2 piovdd output current (i ol2 ) = 6.5ma piovdd output current (i ol2 ) = 2.5ma www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 19 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 5 pin mapping 5.1 intel 80 data pins this function is controlled by cnf [1:0] table 5-1: S1D13742b00 intel 80 data pin mapping pin name 16-bit data no swap (cnf1=1, cnf0=1) 16-bit data swapped (cnf1=1, cnf0=0) 8-bit data no swap (cnf1=0, cnf0=1) 8-bit data swapped (cnf1=0, cnf0=0) md15 md15 md0 pulled low by internal resistor pulled low by internal resistor ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? md8 md8 md7 pulled low by internal resistor pulled low by internal resistor md7 md7 md8 md7 md0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? md0 md0 md15 md0 md7 table 5-2: S1D13742b01 intel 80 data pin mapping pin name 16-bit data no swap (cnf1=1, cnf0=1) 16-bit data swapped (cnf1=1, cnf0=0) 8-bit data no swap (cnf1=0, cnf0=1) 8-bit data swapped (cnf1=0, cnf0=0) md15 md15 md0 hi-z hi-z ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? md8 md8 md7 hi-z hi-z md7 md7 md8 md7 md0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? md0 md0 md15 md0 md7 www.datasheet.co.kr datasheet pdf - http://www..net/
page 20 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 5.2 lcd interface pin mapping table 5-3: lcd interface pin mapping for mode 1 and mode 2 pin name 16bpp 18bpp single (18-bit) double (36-bit) single (18-bit) double (36-bit) normal swap normal swap normal swap normal swap vs vertical sync hs horizontal sync pclk pixel clock de data enable vd0b4r4b4r4b0 r5 b0r5 vd1b0r3b0r3b1 r4 b1r4 vd2b1r2b1r2b2 r3 b2r3 vd3b2r1b2r1b3 r2 b3r2 vd4b3r0b3r0b4 r1 b4r1 vd5b4r4b4r4b5 r0 b5r0 vd6g0g5g0g5g0 g5 g0g5 vd7g1g4g1g4g1 g4 g1g4 vd8g2g3g2g3g2 g3 g2g3 vd9g3g2g3g2g3 g2 g3g2 vd10 g4 g1 g4 g1 g4 g1 g4 g1 vd11 g5 g0 g5 g0 g5 g0 g5 g0 vd12 r4 b4 r4 b4 r0 b5 r0 b5 vd13 r0 b3 r0 b3 r1 b4 r1 b4 vd14 r1 b2 r1 b2 r2 b3 r2 b3 vd15 r2 b1 r2 b1 r3 b2 r3 b2 vd16 r3 b0 r3 b0 r4 b1 r4 b1 vd17 r4 b4 r4 b4 r5 b0 r5 b0 vd18 driven 0 driven 0 b4 r4 driven 0 driven 0 b0 r5 vd19 driven 0 driven 0 b0 r3 driven 0 driven 0 b1 r4 vd20 driven 0 driven 0 b1 r2 driven 0 driven 0 b2 r3 vd21 driven 0 driven 0 b2 r1 driven 0 driven 0 b3 r2 vd22 driven 0 driven 0 b3 r0 driven 0 driven 0 b4 r1 vd23 driven 0 driven 0 b4 r4 driven 0 driven 0 b5 r0 vd24 driven 0 driven 0 g0 g5 driven 0 driven 0 g0 g5 vd25 driven 0 driven 0 g1 g4 driven 0 driven 0 g1 g4 vd26 driven 0 driven 0 g2 g3 driven 0 driven 0 g2 g3 vd27 driven 0 driven 0 g3 g2 driven 0 driven 0 g3 g2 vd28 driven 0 driven 0 g4 g1 driven 0 driven 0 g4 g1 vd29 driven 0 driven 0 g5 g0 driven 0 driven 0 g5 g0 vd30 driven 0 driven 0 r4 b4 driven 0 driven 0 r0 b5 vd31 driven 0 driven 0 r0 b3 driven 0 driven 0 r1 b4 vd32 driven 0 driven 0 r1 b2 driven 0 driven 0 r2 b3 vd33 driven 0 driven 0 r2 b1 driven 0 driven 0 r3 b2 vd34 driven 0 driven 0 r3 b0 driven 0 driven 0 r4 b1 vd35 driven 0 driven 0 r4 b4 driven 0 driven 0 r5 b0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 21 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 5.3 lcd interface data pins this function is controlled by reg[14h] bit 7. table 5-4: lcd interface data pin mapping pin name 36-bit data no swap reg[14] b7=0 36-bit data swapped reg[14] b7=1 18-bit data no swap reg[14] b7=0 18-bit data swapped reg[14] b7=1 vd35 vd35 vd0 driven low driven low ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vd18 vd18 vd17 driven low driven low vd17 vd17 vd18 vd17 vd0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vd0 vd0 vd35 vd0 vd17 www.datasheet.co.kr datasheet pdf - http://www..net/
page 22 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 6 d.c. characteristics 6.1 absolute maximum ratings 6.2 recommended operating conditions note there are no special power on/off requirements with respect to sequencing the various vdd pins. there are also no special requirements for the io signals, however inputs should not be floating. if the input signals were to power up in a valid cycle, the S1D13742 would decode the cycle. table 6-1: absolute maximum ratings symbol parameter rating units core v dd core supply voltage vss - 0.3 ~ 2.0 v pll v dd pll supply voltage vss - 0.3 ~ 2.0 v io v dd host io supply voltage corevdd ~ 4.0 v pio v dd panel io supply voltage corevdd ~ 4.0 v v in input signal voltage vss - 0.3 ~ iovdd + 0.3 v v out output signal voltage vss - 0.3 ~ iovdd + 0.3 v i out output signal current 10 ma table 6-2: recommended operating conditions symbol parameter condition min typ max units core v dd core supply voltage vss = 0 v 1.40 1.50 1.60 v pll v dd pll supply voltage vss = 0 v 1.40 1.50 1.60 v io v dd host io supply voltage vss = 0 v 1.65 ? 3.6 v pio v dd panel io supply voltage vss = 0 v 1.65 ? 3.6 v v in input voltage ? vss ? iovdd v t opr operating temperature ? -40 +25 +85 c www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 23 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 6.3 electrical characteristics the following characteristics are for: iovdd. vss = 0v, t opr = -40 to +85 c. note 1. typical operating current environment: 352x416 k2 tft panel with pclk divide by 4. sysclk=48.5mhz from pll, pll source from 19.2mhz clki input. 18bpp memory storage. corevdd and pllvdd to 1.5v, hiovdd, piovdd to 1.8v 2. typical operating current environment: 800 x 480 tft panel with pclk divide by 3. sysclk= 59mhz from pll, pll source from 12mhz clki input. 16bpp memory storage. corevdd and pllvdd to 1.5v, hiovdd, piovdd to 1.8v table 6-3: electrical characteristics for iovdd or piovdd = 1.8v 0.15v symbol parameter condition min typ max units i qall quiescent current clki stopped (grounded), sleep mode enabled, all power supplies active ? 100 ? a i pll pll current f pll = 54mhz ? 500 1000 a i core operation peak current corevdd power pin ? ? 62 ma p core core typical operating power see note 1 ?9.15?mw p pll pll typical operating power ? 0.7 ? mw p pio pio typical operating power ? 2.8 ? mw p hio hio typical operating power ? 0.018 ? mw p core core typical operating power see note 2 ? 10.9 ? mw p pll pll typical operating power ? 0.77 ? mw p pio pio typical operating power ? 2.124 ? mw p hio hio typical operating power ? 0.001 ? mw i iz input leakage current ? -5 ? 5 a i oz output leakage current ? -5 ? 5 a iov oh2 high level output voltage iov dd = min i oh2 = -2.5ma iovdd - 0.40 ? iovdd v piov oh2 high level output voltage piovdd = min i oh2 = -2.5ma piovdd - 0.40 ? piovdd v piov oh4 high level output voltage piovdd = min i oh2 = -6.5ma piovdd - 0.40 ? piovdd v iov ol2 low level output voltage iovdd = min i ol2 = 2.5ma vss ? 0.40 v piov ol2 low level output voltage piovdd = min i ol2 = 2.5ma vss ? 0.40 v piov ol4 low level output voltage piovdd = min i ol2 = 6.5ma vss ? 0.40 v iov ih high level input voltage cmos input 1.27 ? ? v piov ih high level input voltage cmos input 1.27 ? ? v iov il low level input voltage cmos input ? ? 0.57 v piov il low level input voltage cmos input ? ? 0.57 v iov t+ positive trigger voltage cmos schmitt 0.57 ? 1.56 v iov t- negative trigger voltage cmos schmitt 0.33 ? 1.27 v io v h hysteresis voltage cmos schmitt 0.24 ? ? v r pu1 pull-up resistance type1 v i = vss 40 100 240 k r pd1 pull-down resistance type1 v i = vdd 40 100 240 k r pu2 pull-up resistance type2 v i = vss 80 200 480 k r pd2 pull-down resistance type2 v i = vdd 80 200 480 k c io pin capacitance f = 1mhz, vdd = 0v ? ? 8 pf www.datasheet.co.kr datasheet pdf - http://www..net/
page 24 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential the following characteristics are for: iovdd. vss = 0v, t opr = -40 to +85 c. note 1. typical operating current environment: 352x416 k2 tft panel with pclk divide by 4. sysclk=48.5mhz from pll, pll source from 19.2mhz clki input. 18bpp memory storage. corevdd and pllvdd to 1.5v, hiovdd, piovdd to 2.8v 2. typical operating current environment: 800 x 480 tft panel with pclk divide by 3. sysclk= 59mhz from pll, pll source from 12mhz clki input. 16bpp memory storage. corevdd and pllvdd to 1.5v, hiovdd, piovdd to 2.8v table 6-4: electrical characteristics for iovdd or piovdd = 2.8v 0.14v symbol parameter condition min typ max units i qall quiescent current clki stopped (grounded), sleep mode enabled, all power supplies active ?120? a i pll pll current f pll = 54mhz ? 500 1000 a i core operation peak current corevdd power pin ? ? 62 ma i iz input leakage current ? -5 ? 5 a i oz output leakage current ? -5 ? 5 a iov oh2 high level output voltage iov dd = min i oh2 = -3.6ma iovdd - 0.40 ? iovdd v piov oh2 high level output voltage piovdd = min i oh2 = -3.6ma piovdd - 0.40 ?piovddv piov oh4 high level output voltage piovdd = min i oh2 = -10.8ma piovdd - 0.40 ?piovddv iov ol2 low level output voltage iovdd = min i ol2 = 3.6ma vss ? 0.40 v piov ol2 low level output voltage piovdd = min i ol2 = 3.6ma vss ? 0.40 v piov ol4 low level output voltage piovdd = min i ol2 = 10.8ma vss ? 0.40 v iov ih high level input voltage cmos input 1.75 ? ? v piov ih high level input voltage cmos input 1.75 ? ? v iov il low level input voltage cmos input ? ? 0.70 v piov il low level input voltage cmos input ? ? 0.70 v iov t+ positive trigger voltage cmos schmitt 0.93 ? 2.36 v iov t- negative trigger voltage cmos schmitt 0.53 ? 1.92 v io v h hysteresis voltage cmos schmitt 0.40 ? ? v r pu1 pull-up resistance type1 v i = vss 24 60 144 k r pd1 pull-down resistance type1 v i = vdd 24 60 144 k r pu2 pull-up resistance type2 v i = vss 48 120 288 k r pd2 pull-down resistance type2 v i = vdd 48 120 288 k c io pin capacitance f = 1mhz, vdd = 0v ? ? 8 pf www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 25 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential the following characteristics are for: iovdd, vss = 0v, t opr = -40 to +85 c. table 6-5: electrical characteristics for iovdd or piovdd = 3.3v 0.3v symbol parameter condition min typ max units i qall quiescent current quiescent conditions ? 160 ? a i pll pll current f pll = 54mhz ? 500 1000 a i core operation peak current corevdd power pin ? ? 62 ma i iz input leakage current ? -5 ? 5 a i oz output leakage current ? -5 ? 5 a iov oh2 high level output voltage iov dd = min i oh2 = -4.0ma iovdd - 0.40 ? iovdd v piov oh2 high level output voltage piovdd = min i oh2 = -4.0ma piovdd - 0.40 ?piovddv piov oh4 high level output voltage piovdd = min i oh2 = -12.0ma piovdd - 0.40 ?piovddv iov ol2 low level output voltage iovdd = min i ol2 = 4.0ma vss ? 0.40 v piov ol2 low level output voltage piovdd = min i ol2 = 4.0ma vss ? 0.40 v piov ol4 low level output voltage piovdd = min i ol2 = 12.0ma vss ? 0.40 v iov ih high level input voltage cmos input 2.20 ? ? v piov ih high level input voltage cmos input 2.20 ? ? v iov il low level input voltage cmos input ? ? 0.80 v piov il low level input voltage cmos input ? ? 0.80 v iov t+ positive trigger voltage cmos schmitt 1.40 ? 2.70 v iov t- negative trigger voltage cmos schmitt 0.60 ? 1.80 v io v h hysteresis voltage cmos schmitt 0.45 ? ? v r pu1 pull-up resistance type1 v i = vss 20 50 120 k r pd1 pull-down resistance type1 v i = vdd 20 50 120 k r pu2 pull-up resistance type2 v i = vss 40 100 240 k r pd2 pull-down resistance type2 v i = vdd 40 100 240 k c io pin capacitance f = 1mhz, vdd = 0v ? ? 8 pf www.datasheet.co.kr datasheet pdf - http://www..net/
page 26 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7 a.c. characteristics conditions: iovdd = piovdd = 1.8v 0.15v or 2.8v 0.14v t a = -40 c to 85 c t rise and t fall for all inputs except schmitt and clki must be < 50 ns (10% ~ 90%) t rise and t fall for all schmitt must be < 5 ms (10% ~ 90%) c l = 8pf ~ 30pf (md[15:0]) c l = 15pf (te, gpio_int, clkout) c l = 30pf (lcd panel/gpio interface) 7.1 clock timing 7.1.1 input clocks figure 7-1 clock input required (clki) 90% 10% v ih v il t1 t2 t3 t4 t osc t osc t osc t5 clki clki www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 27 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 1. t6 = 2*t osc 2. the input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). 3. the input clock cycle jitter is the difference in period between adjacent cycles. 4. the jitter characteristics must satisfy both the t5 and t6 characteristics 5. input duty cycle is not critical and can be 40/60 6. the minimum system clock frequency required for correct operation depends on the cycle length of the intel 80 interface. see section 8.4, ?setting sysclk and pclk? on page 43 for more details. 7.1.2 pll clock the pll circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. noise on the clock or the supplied power may cause the operation of the pll circuit to become unstable or increase the jitter. due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the pll be isolated from those of other power supplies. filtering should also be used to keep the power as clean as possible. the jitter of the input clock waveform should be as small as possible. table 7-1 clock input requirements (clki) symbol parameter min typ max units f osc (see note 6) input clock frequency - pll used for system clock 1 ? 66 mhz input clock frequency - clki used for system clock 0 ? 68.90 mhz t osc input clock period ? 1/f osc ? s t1 input clock pulse width high 0.4t osc ?0.6t osc s t2 input clock pulse width low 0.4t osc ?0.6t osc s t3 input clock rise time (10% - 90%) ? ? 5.0 ns t4 input clock fall time (90% - 10%) ? ? 5.0 ns t5 input clock period jitter (see notes 2 and 4) -300 300 ps t6 (see note 1) input clock cycle jitter (see notes 3 and 4) -300 300 ps www.datasheet.co.kr datasheet pdf - http://www..net/
page 28 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential figure 7-2: pll start-up time 1 refer to section 8.4, ?setting sysclk and pclk? on page 43. table 7-2: pll clock requirements symbol parameter min max units f pll pll output clock frequency 44.26 1 66.95 mhz t pjref pll output clock period jitter -3 3 % t pduty pll output clock duty cycle 40 60 % t pstal pll output stable time ? 10 ms mhz pll xxmhz output (xx = 44.26~66.95mhz) 10 ms note: pll minimum frequency = 44.26mhz pll maximum frequency = 66.95mhz the pll frequency will ramp between the off state and the programmed frequency. to guarantee the lowest possible clock jitter, 10ms is required for stabilization. jitter (ns) time (ms) pll enable lock in time lock in time reference clock 10 ms pll stable (based on intel 80 cycle length. refer to section 8.4 for more information) www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 29 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 7.2 reset# timing figure 7-3 S1D13742 reset# timing table 7-3 S1D13742 reset# timing symbol parameter min max units t1 active reset pulse width 1 ? clki t1 reset# clki t clki www.datasheet.co.kr datasheet pdf - http://www..net/
page 30 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.3 host interface timing 7.3.1 intel 80 interface timing - 1.8 volt figure 7-4: intel 80 input a.c. characteristics - 1.8 volt d/c# cs# we# md [15:0] write rd# md[ 15:0 ] read t ast t wah t wcs t csf t csf t wc t wl t wh t dst t dht t rcs t rc t rl t rh t rah t rodh t rdd note 1: the d/c# input pin is used to distinguish between address and data. note 2: the cs# pin can be kept low between write and read pulses as the register addresses will auto-increment. the register address will auto-increment in word increments for all register access except the memory data port. writes to the memory data port will not increment the register address to support burst data writes to memory. t rdv t rrdz t ch t ch t w2r t r2w t crdz t codh (note 1) (note 2) (note 3) (note 3) note 3: when cnf1=0, only md[7:0] are used. when cnf1=1, md[15:0] are used for accesses to the memory data port. md[7:0] are used for all other accesses. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 31 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential note 1. for a read cycle after a write cycle, md[15:0] must be driven hi-z a maximum of t rdd after the falling edge of rd#. 2. for a write cycle after a read cycle, md[15:0] should not be driven by the host until t rrdz after the rising edge of rd#. 3. when cnf1=0, only md[7:0] are used. when cnf1=1, md[7:0] are used for all accesses except for the memory data port when md[15:0] are used. table 7-4: intel 80 input a.c. characteristics - 1.8 volt signal symbol parameter min max unit description d/c# t ast address setup time (read/write) 1 ? ns t wah address hold time (write) 5 ? ns t rah address hold time (read) 29 ? ns cs# t wcs chip select setup time (write) t wl ?ns t rcs chip select setup time (read) t rl ?ns t ch chip select hold time (read/write) 0 ? ns t csf chip select wait time (read/write) 1 ? ns we# t wc register write cycle 12 ? ns lut write cycle 2sysclk + 1 ? ns memory write cycle 2sysclk + 1 ? ns t wl pulse low duration 5 ? ns t wh pulse high duration t wc - t wl ?ns t w2r wr# rising edge to rd# falling edge 11 ? ns note 1 rd# t r2w rd# rising edge to wr# falling edge 26 ? ns note 2 t rc read cycle t rl + t rh ?ns t rl pulse low duration t rdv ?ns t rh pulse high duration for registers 35 ? ns pulse high duration for memory and lut 1sysclk + 26 ? ns md[15:0] (note 3) t dst write data setup time 4 ? ns t dht write data hold time 5 ? ns t rodh read data hold time from rd# rising edge 11 ? ns t rrdz rd# rising edge to md hi-z ? 31 ns t codh read data hold time from cs# rising edge 1 ? ns t crdz cs# rising edge to md hi-z ? 8 ns t rdv rd# falling edge to md valid for registers ? 16 ns cl=30pf rd# falling edge to md valid for lut ? 4sysclk + 26 ns rd# falling edge to md valid for memory ? 5sysclk + 19 ns rd# falling edge to md valid for registers ? 11 ns cl = 8pf rd# falling edge to md valid for lut ? 4sysclk + 21 ns rd# falling edge to md valid for memory ? 5sysclk + 14 ns t rdd rd# falling edge to md driven 4 ? ns cl=30pf rd# falling edge to md driven 3 ? ns cl = 8pf www.datasheet.co.kr datasheet pdf - http://www..net/
page 32 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.3.2 intel 80 interface timing - 3.3 volt figure 7-5: intel 80 input a.c. characteristics - 3.3 volt d/c# cs# we# md[ 15:0 ] write rd# md[ 15:0 ] read t ast t wah t wcs t csf t csf t wc t wl t wh t dst t dht t rcs t rc t rl t rh t rah t rodh t rdd note 1: the d/c# input pin is used to distinguish between address and data. note 2: the cs# pin can be kept low between write and read pulses as the register addresses will auto-increment. the register address will auto-increment in word increments for all register access except the memory data port. writes to the memory data port will not increment the register address to support burst data writes to memory. t rdv t rrdz t ch t ch t w2r t r2w t crdz t codh (note 1) (note 2) (note 3) (note 3) note 3: when cnf1=0, only md[7:0] are used. when cnf1=1, md[15:0] are used for accesses to the memory data port. md[7:0] are used for all other accesses. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 33 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential note 1. for a read cycle after a write cycle, md[15:0] must be driven hi-z a maximum of t rdd after the falling edge of rd#. 2. for a write cycle after a read cycle, md[15:0] should not be driven by the host until t rrdz after the rising edge of rd#. 3. when cnf1=0, only md[7:0] are used. when cnf1=1, md[7:0] are used for all accesses except for the memory data port when md[15:0] are used. table 7-5: intel 80 input a.c. characteristics - 3.3 volt signal symbol parameter min max unit description d/c# t ast address setup time (read/write) 1 ? ns t wah address hold time (write) 5 ? ns t rah address hold time (read) 29 ? ns cs# t wcs chip select setup time (write) t wl ?ns t rcs chip select setup time (read) t rl ?ns t ch chip select hold time (read/write) 0 ? ns t csf chip select wait time (read/write) 1 ? ns we# t wc register write cycle 12 ? ns lut write cycle 2sysclk + 1 ? ns memory write cycle 2sysclk + 1 ? ns t wl pulse low duration 5 ? ns t wh pulse high duration t wc - t wl ?ns t w2r wr# rising edge to rd# falling edge 16 ? ns note 1 rd# t r2w rd# rising edge to wr# falling edge 26 ? ns note 2 t rc read cycle t rl + t rh ?ns t rl pulse low duration t rdv ?ns t rh pulse high duration for registers 36 ? ns pulse high duration for memory and lut 1sysclk + 26 ? ns md[15:0] (note 3) t dst write data setup time 4 ? ns t dht write data hold time 5 ? ns t rodh read data hold time from rd# rising edge 11 ? ns t rrdz rd# rising edge to md hi-z ? 31 ns t codh read data hold time from cs# rising edge 1 ? ns t crdz cs# rising edge to md hi-z ? 8 ns t rdv rd# falling edge to md valid for registers ? 11 ns cl=30pf rd# falling edge to md valid for lut ? 4sysclk + 21 ns rd# falling edge to md valid for memory ? 5sysclk + 14 ns rd# falling edge to md valid for registers ? 9 ns cl = 8pf rd# falling edge to md valid for lut ? 4sysclk + 18 ns rd# falling edge to md valid for memory ? 5sysclk + 11 ns t rdd rd# falling edge to md driven 3 ? ns cl=30pf rd# falling edge to md driven 2 ? ns cl = 8pf www.datasheet.co.kr datasheet pdf - http://www..net/
page 34 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.3.3 definition of transition time to hi-z state due to the difficulty of hi-z impedance measurement for high speed signals, transition time from high/low to hi-z specified as follows. ? high to hi-z delay time: t phz , delay time when a gate voltage of final stage of the pch-mosfet turns to 0.8 x iovdd (pch-mosfet is off). total delay time to hi-z is calculated as follows: internal logic delay + t phz (from high to hi-z) ? low to hi-z delay time: t plz , delay time when a gate voltage of final stage of the nch- mosfet turns to 0.2 x iovdd (nch-mosfet is off). total delay time to hi-z is calculated as follows: internal logic delay + t phz (from high to hi-z) the functional model of a final stage of the tri state output cell is shown in figure 7-6: ?definition of transition time to hi-z state?. figure 7-6: definition of transition time to hi-z state en a x p n iovdd vss to measure t phz to measure t plz en ? iovdd t phz 0.8 iovdd iovdd volt p time en ? iovdd t plz 0.2 iovdd iovdd volt n time tri state output cell www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 35 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 7.4 display interface the timing parameters required to drive a flat panel display are shown below. timing details for each supported panel type are provided in the remainder of this section. note all timing measurements are taken to/from the ?piovdd level in the following dis- play interface timing diagrams. figure 7-7: panel timing parameters note ts = 1/pclk table 7-6: panel timing parameter definition and register summary symbol description derived from units hdisp horizontal display width (reg[16h] bits 6-0) x 8 ts hndp horizontal non-display period (reg[18h] bits 6-0) hps hs pulse start position reg[22h] bits 6-0 hsw hs pulse width (reg[20h] bits 6-0) vdisp vertical display height (reg[1ch] bits 1-0, reg[1ah] bits 7-0) lines (ht) vndp vertical non-display period reg[1eh] bits 7-0 vps vs pulse start position reg[26h] bits 7-0 vsw vs pulse width reg[24h] bits 6-0 vdisp hdisp hps de hdisp vsw hsw hndp vps vdisp vndp te te ht de www.datasheet.co.kr datasheet pdf - http://www..net/
page 36 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.4.1 tft power-on sequence figure 7-8: tft power-on sequence timing table 7-7: tft power-on sequence timing symbol parameter min max units t1 power save mode disabled to lcd signals active 020ns lcd signals*** power save t1 **the lcd power-on sequence is activated by programming the power save register (reg[56h]) bit 1 or bit 0 to 0. ***lcd signals include: vd[35:0], pclk, hs, vs, and de. (reg[56h] bits 1-0) mode enable** www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 37 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 7.4.2 tft power-off sequence figure 7-9: tft power-off sequence timing table 7-8: tft power-off sequence timing symbol parameter min max units t1 power save mode enabled to lcd signals low 020ns lcd signals*** **the lcd power-off sequence is activated by programming the power save register (reg[56h]) bit 1 or bit 0 to 1. ***lcd signals include: vd[35:0], pclk, hs, vs, and de. t1 power save (reg[56h] bits 1-0) mode enable** www.datasheet.co.kr datasheet pdf - http://www..net/
page 38 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 7.4.3 18/36-bit tft panel timing figure 7-10: 18/36-bit tft a.c. timing note hs, vs, pclk all have polarity select bits via registers t3 t5 hs t1 t4 vs de pclk 320 t2 hs 2 1 t13 t10 t11 t14 t15 t16 t7 t8 t9 t12 vd[17:0] note: 2 pixels/clock mode t6 invalid invalid n+1 3-4 1-2 vd[35:0] invalid invalid note: 1 pixel/clock mode pclk t13 t10 t11 t14 t9 t12 reg[28h] b7=1 reg[28h] b7=0 de t17 t18 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 39 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 1. ts = pixel clock period note in 36-bit mode, the data is always guaranteed to be launched on the correct edge of pclk. in this mode, the frequency of pclk is ? the programmed internal value. if it is desired that hs and vs are always launched on the same edge of pclk as the data, then hndp, hsw, and hss should be programmed with even values. table 7-9: 18/36-bit tft a.c. timing symbol parameter min typ max units t1 vs cycle time ? vdisp + vndp ? lines t2 vs pulse width low ? vsw ? lines t3 vs falling edge to hs falling edge phase difference ? hps ? ts t4 hs cycle time ? hdisp + hndp ? ts t5 hs pulse width low ? hsw ? ts t6 hs falling edge to de active ? hndp-hps ? ts t7 de pulse width ? hdisp ? ts t8 de falling edge to hs falling edge ? hps ? ts t9 pclk period 1 ? ? ts t10 pclk pulse width low 0.5 ? ? ts t11 pclk pulse width high 0.5 ? ? ts t12 hs setup to pclk active edge 0.5 ? ? ts t13 de to pclk rising edge setup time 0.5 ? ? ts t14 de hold from pclk active edge 0.5 ? ? ts t15 data setup to pclk active edge 0.5 ? ? ts t16 data hold from pclk active edge 0.5 ? ? ts t17 de stop setup to vs start ? vps ? ts t18 vertical non-display period ? vndp ? ts www.datasheet.co.kr datasheet pdf - http://www..net/
page 40 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 8 clocks 8.1 clock descriptions figure 8-1: S1D13742 clock block diagram clki external clock source pll internal pll enable clock source select (reg[12h] bit 0) 1 0 sysclk mhz glitch free divider internal 32 1 2 3 clkouten clkout pclk divide select (reg[12h] bits 7-3) ? ? ? 1 0 pclk external pclk 2 panel data width select (reg[14h] bit 0) www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 41 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 8.2 pll block diagram figure 8-2: pll block diagram cp vc amon vcp vco mux loop filter rs cs cp pfd m-divider clki tck l-counter n-counter v-divider mux sysclk tout 1/32 refck mux pfd = phase frequency detector cp = charge pump vco = voltage controlled oscillator loop filter = low pass filter test control = internal control logic where: reg[04h] reg[08h] reg[0ah] reg[0ah] reg[0ch] reg[0eh] reg[08h] pllclk www.datasheet.co.kr datasheet pdf - http://www..net/
page 42 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 8.3 clocks versus functions this table lists the internal clocks required for the following S1D13742 functions. note register access does not require an internal clock as the S1D13742 creates a clock from the bus cycle alone. internal clock requirements function internal sysclk internal pclk register read/write no no memory read/write yes no look-up table register read/write yes no power save no no lcd output yes yes www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 43 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 8.4 setting sysclk and pclk the period of the system clock, t sysclk , must be set such that it falls within the following range: 14.94ns < t sysclk < (t bbc - 0.914) x 0.485 ns where t bbc is the minimum back-to-back cycle time of the intel 80 interface. for example, if the minimum back-to-back cycle time of the intel 80 interface is 5 x 9.5 = 47.5ns, then: 14.94ns < t sysclk < 22.594ns therefore, 44.26mhz < f sysclk < 66.95mhz care should be taken when setting t sysclk so that the desired pclk frequency, f pclk , can be achieved. pclk is an integer divided version of sysclk. the following graph shows the suggested setting for sysclk for a given value of pclk for t bbc = 47.5ns. figure 8-3: setting of sysclk for a desired pclk 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 6 8 10 12 14 16 18 20 22 24 26 pclk frequency (mhz) sysc l k f r equ e n cy ( m hz ) sysclk/2 sysclk/3 sysclk/4 sysclk/5 sysclk/6 sysclk/7 www.datasheet.co.kr datasheet pdf - http://www..net/
page 44 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9 registers this section discusses how and where to access the S1D13742 registers. it also provides detailed information about the layout and usage of each register. burst data writes to the register space is supported. this applies to all register write access except the memory data port (reg[48h - 49h]) and the gamma correction table data register [reg[54h]). all writes to these two registers will auto-increment the internal memory address only. 9.1 register mapping all registers and memory are accessed via the intel 80 interface. all access is 8-bit only except for the memory data port (reg[48h - 49h]) which is accessed as 16-bit (if cnf1=1) or 8-bit (if cnf1=0). www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 45 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 9.2 register set the S1D13742 registers are listed in the following table. table 9-1: S1D13742 register set register pg register pg read-only configuration registers reg[00h] revision code register 46 reg[02h] configuration readback register 46 clock configuration registers reg[04h] pll m-divider register 47 reg[06h] pll setting register 0 48 reg[08h] pll setting register 1 48 reg[0ah] pll setting register 2 48 reg[0ch] pll setting register 3 48 reg[0eh] pll setting register 4 49 reg[10h] 49 reg[12h] clock source select register 50 panel configuration registers reg[14h] panel type register 52 reg[16h] horizontal display width register (hdisp) 52 reg[18h] horizontal non-display period register (hndp) 52 re g[1ah] vertical display height register 0 (vdisp) 53 reg[1ch] vertical display height register 1 (vdisp) 53 reg[1eh] vertical non-display period register (vndp) 53 reg[20h] hs pulse width register (hsw) 53 reg[22h] hs pulse start position register 0 (hps) 54 reg[24h] vs pulse width register (vsw) 54 reg[26h] vs pulse start position register 0 (vps) 54 reg[28h] pclk polarity register 54 input mode register reg[2ah] input mode register 55 reg[2ch] input yuv/rgb translate mode register 0 57 reg[2eh] yuv/rgb translate mode register 1 57 reg[30h] u data fix register 59 reg[32h] v data fix register 59 display mode registers reg[34h] display mode register 60 reg[36h] special effects register 61 window settings reg[38h] window x start position register 0 64 reg[3ah] window x start position register 1 64 reg[3ch] window y start position register 0 64 reg[3eh] window y start position register 1 64 reg[40h] window x end position register 0 65 reg[42h] window x end position register 1 65 reg[44h] window y end position register 0 65 reg[46h] window y end position register 1 65 memory access reg[48h] memory data port register 0 66 reg[49h] memory data port register 1 66 reg[4ah] memory read address register 0 67 re g[4ch] memory read address register 1 67 reg[4eh] memory read address register 2 67 gamma correction registers reg[50h] gamma correction enable register 68 reg[52h] gamma correction table index register 69 reg[54h] gamma correction table data register 69 miscellaneous registers reg[56h] power save register 70 reg[58h] non-display period control / status register 70 general purpose io pins registers reg[5ah] general purpose io pins configuration register 0 72 reg[5ch] general purpose io pins status/control register 0 72 reg[5eh] gpio positive edge interrupt trigger register 72 reg[60h] gpio negative edge interrupt trigger register 73 reg[62h] gpio interrupt status register 73 reg[64h] gpio pull down control register 0 73 www.datasheet.co.kr datasheet pdf - http://www..net/
page 46 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3 register descriptions all reserved bits must be set to the default value. writing a non-default value to a reserved bit may produce undefined results. bits marked as n/a have no hardware effect. unless specified otherwise, all register bits are set to 0 during power-on reset. 9.3.1 read-only configuration registers bits 7-2 product code bits [5:0] these are read-only bits that indicates the product code. the product code is 100000b. bits 1-0 revision code bits [1:0] these are read-only bits that indicates the revision code. the revision code for the S1D13742b00 is 00b, and for the S1D13742b01 is 01b. bits 2-0 cnf[2:0] status these read-only status bits return the status of the configuration pins cnf[2:0]. reg[00h] revision code register default = 80h for S1D13742b00 or 81h for S1D13742b01 read only product code bits 5-0 revision code bits 1-0 76543210 reg[02h] configuration readback register default = xxh read only n/a cnf2 status cnf1 status cnf0 status 7 6 5 4 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 47 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 9.3.2 clock configuration registers bit 7 pll lock bit (read only) when this bit = 0, the pll output is not stable. in this state r/w access to the display buffer is prohibited. when this bit = 1, the pll output is stable. bits 5-0 m-divider bits [5:0] these bits determine the divide ratio between clki and the actual input clock to the pll note the internal input clock to the pll (pllclk) must be between 1 mhz and 2 mhz. de- pending on clki, these bits will have to be set accordingly. note values higher then 20h are not allowed. reg[04h] pll m-divider register default = 00h read/write pll lock bit (ro) n/a m-divider bits 5-0 7 6543210 table 9-2: pll m-divide selection reg[04h] bits 5-0 m-divide ratio 0h 1:1 01h 2:1 02h 3:1 03h 4:1 ? ? ? ? ? ? 20h 33:1 21h to 3fh reserved www.datasheet.co.kr datasheet pdf - http://www..net/
page 48 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential this register must be programmed with the value f8h. this register must be programmed with the value 80h. this register must be programmed with the value 28h. this register must be programmed with the value 00h. reg[06h] pll setting register 0 default = 00h read/write pll setting register 0 bits 7-0 76543210 reg[08h] pll setting register 1 default = 00h read/write pll setting register 1 bits 7-0 76543210 reg[0ah] pll setting register 2 default = 00h read/write pll setting register 2 bits 7-0 76543210 reg[0ch] pll setting register 3 default = 00h read/write pll setting register 3 bits 7-0 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 49 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bits 6-0 l-counter bits [6:0] these bits are used to configure the pll output (in mhz) and must be set according to the following formula. pll output = (l-counter +1) x pllclk = ll x pllclk where: pll output is the desired pll output frequency (in mhz). l-counter is the value of this register (in decimal). pllclk is the internal input clock to the pll (in mhz). please refer to section 8.4, ?setting sysclk and pclk? on page 43 for restrictions on pll output frequencies. writes to this register have no effect on hardware. during auto increment, a dummy write needs to be performed to this register. reg[0eh] pll setting register 4 default = 00h read/write n/a l-counter bits 6-0 76543210 table 9-3 pll setting example target frequency (mhz) ll clki input clock (mhz) m-divider reg[04] bits 5-0 m-divide ratio pllclk (mhz) pout (mhz) 53 53 12 0bh 12:1 1.0 53 60 60 12 0bh 12:1 1.0 60 ? ?????? 53 53 19.2 12h 19:1 1.0105 53.53 60 60 19.2 12h 19:1 1.0105 60.63 reg[10h] default = 00h read/write n/a 7 6 5 4 3 2 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
page 50 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential bits 7-3 pclk divide select bits [5:0] these bits specify the divide ratio for the panel clock (pclk). the clock source for pclk is sysclk. all resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio. reg[12h] clock source select register default = 00h read/write pclk divide select bits 4-0 n/a sysclk source select 76543 2 10 table 9-4 pclk divide ratio selection reg[0012h] bits 7-3 pclk divide ratio 00h reserved 01h 2:1 02h 3:1 03h 4:1 04h 5:1 05h 6:1 06h 7:1 07h 8:1 08h 9:1 09h 10:1 0ah 11:1 0bh 12:1 0ch 13:1 0dh 14:1 0eh 15:1 0fh 16:1 10h 17:1 11h 18:1 ? ? ? ? ? ? 1fh 32:1 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 51 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bit 0 sysclk source select this bit selects the system clock (sysclk) source for the controller. when this bit = 0, the sysclk source is the external clki input. when this bit = 1, the sysclk source is the internal pll. if the pll is selected as the sysclk source (bit 0 = 1), the pll must be configured using reg[06h], reg[08h], reg[0ah], reg[0ch], reg[0eh] and reg[10h] before setting this bit. note to use pll as system clock source (sysclk), sleep mode needs to be first enabled, reg[56h] bit 1 = 1. once in sleep mode, reg[04h] and reg[0eh] can be changed to set the desired pll frequency. once reg[04h] and reg[0eh] have been set, reg[12h] bit 0 can be set to 1b to select pll as the system clock source. the pll out- put will only be active after exiting the sleep mode (reg[56h] bit 1 = 0). the pll out- put will become stable after 10msec. the display memory or the gamma correction table must not be accessed before this time. reg[04h] bit 7, the pll lock bit, can be used to determine if the pll output is stable. www.datasheet.co.kr datasheet pdf - http://www..net/
page 52 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.3 panel configuration registers bit 7 vd data swap when this bit = 0, data lines are normal (i.e.: output pin vd35 = vd35, etc.) when this bit = 1, data lines are swapped (i.e.: output pin vd35 = vd0, etc.) note the data swap will always go from the msb to the lsb on the active output pins. see ?lcd interface data pins? on page 21. bit 0 panel data width when this bit = 0, the lcd interface is configured as 18-bit. when this bit = 1, the lcd interface is configured as 36-bit. bits 6-0 horizontal display width bits [6:0] these bits specify the lcd panel horizontal display width (hdisp), in 8 pixel resolu- tion. horizontal display width in number of pixels = ((reg[16h] bits 6-0) 8 note minimum value of 8 pixels (register programmed to 1). bits 6-0 horizontal non-display period bits [6:0] these bits specify the horizontal non-display period in pixels. for 36-bit wide panels, there are 2 pixels per external pclk. hndp is calculated using the following formula. hndp = (reg[18h] bits 6-0) note the minimum horizontal non-display period is 3 pixels (reg[18h] bits 6-0 = 03h). hs start + hs width <= hndp reg[14h] panel type register default = 00h read/write vd data swap n/a panel data width 7 6 5 4 3 2 10 reg[16h] horizontal display width register (hdisp) default = 01h read/write n/a horizontal display period bits 6-0 76543210 reg[18h] horizontal non-display period register (hndp) default = 00h read/write n/a horizontal non-display period bits 6-0 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 53 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential reg[1ch] bits 1-0 reg[1ah] bits 7-0 vertical display height bits [9:0] these bits specify the lcd panel vertical display height, in 1 line resolution. vertical display height in number of lines = (reg[1ch] bits 1-0, reg[1ah] bits 7-0) note minimum value = 1 line bits 7-0 vertical non-display period bits [7:0] these bits specify the vertical non-display period for panels in 1 line resolution. note minimum value = 2 lines bit 7 hs pulse polarity this bit selects the polarity of the horizontal sync signal. this bit is set according to the horizontal sync signal of the panel. when this bit = 0, the horizontal sync signal is active low. when this bit = 1, the horizontal sync signal is active high. bits 6-0 hs pulse width bits [6:0] these bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. the horizontal sync signal is typically hs, depending on the panel type. the minimum value for these bits is 1. hs pulse width in number of pixels = (reg[20h] bits 6-0) for 36-bit wide panels, there are 2 pixels per external pclk. reg[1ah] vertical display height register 0 (vdisp) default = 01h read/write vertical display height bits 7-0 76543210 reg[1ch] vertical display height register 1 (vdisp) default = 00h read/write n/a vertical display height bits 9-8 7 6 5 4 3 210 reg[1eh] vertical non-display period register (vndp) default = 01h read/write vertical non-display period bits 7-0 76543210 reg[20h] hs pulse width register (hsw) default = 00h read/write hs pulse polarity hs pulse width bits 6-0 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 54 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential bits 6-0 hs pulse start position bits [6:0] these bits specify the start position of the horizontal sync signal with respect to the start of horizontal non-display period, in 1 pixel resolution. for 36-bit wide panels, there are 2 pixels per external pclk. hps = (reg[22h] bits 6-0) bit 7 vs pulse polarity this bit selects the polarity of the vertical sync signal. this bit is set according to the ver- tical sync signal of the panel. when this bit = 0, the vertical sync signal is active low. when this bit = 1, the vertical sync signal is active high. bits 5-0 vs pulse width bits [5:0] these bits specify the width of the panel vertical sync signal, in 1 line resolution. the ver- tical sync signal is typically vs, depending on the panel type. vs pulse width in number of lines = reg[24h] bits 5-0 bits 7-0 vs pulse start position bits [7:0] these bits specify the start position of the vertical sync signal with respect to the start of vertical non-display period, in 1 line resolution. vps is calculated using the following formula: vps = (reg[26h] bits 7-0) bit 7 pclk polarity when this bit = 0, the pclk outputs data transitions on the rising edge when this bit = 1, the pclk outputs data transitions on the falling edge reg[22h] hs pulse start position register 0 (hps) default = 00h read/write n/a hs pulse start position bits 6-0 76543210 reg[24h] vs pulse width register (vsw) default = 00h read/write vs pulse polarity n/a vs pulse width bits 5-0 7 6543210 reg[26h] vs pulse start position register 0 (vps) default = 00h read/write vs pulse start position bits 7-0 76543210 reg[28h] pclk polarity register default = 00h read/write pclk polarity n/a 7 6 5 4 3 2 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 55 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 9.3.4 input mode register bit 7 memory data format this bit determines how the data is stored in memory when this bit = 0, the data stored in memory is 16 bpp. in this case 18 bpp input data will be truncated to 16 bpp when this bit = 1, the data stored in memory is 18 bpp. in this case 16 bpp input data (as determined by bits 3-0) will be expanded to 18 bpp. note in 18-bpp mode, memory above $a0000h is reserved for 2 bits of each 18 bit pixel. therefore the maximum display resolution supported can be calculated as follows: x x y x 2 640kb in 16-bpp mode the entire 768k byte display buffer is available and therefore the maxi- mum display resolution is x x y x 2 768kb reg[2ah] input mode register default = 01h read/write memory data format n/a input data format 7 6 5 43210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 56 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential bits 4-0 input data format bits [4:0] note for yuv 4:2:2 and yuv 4:2:0 settings, the image width must be a multiple of 2 and 4 respectively. for yuv 4:2:0 the height must be a multiple of 2. for rgb 6:6:6 and rgb 8:8:8 mode 1, if the image width is odd, the red pixel data in the last word in each line will be ignored. the red pixel data will need to be re-written on the following transfer along with the green data. see figure 12-2: ?18 bpp mode 1(r 6-bit, g 6-bit, b 6-bit), 262,144 colors,? on page 79 or figure 12-4: ?24 bpp mode 1(r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors,? on page 81. note for further information on input data format and memory data format, see section 11, ?intel 80, 8-bit interface color formats? on page 75, section 12, ?intel 80, 16-bit inter- face color formats? on page 78 and section 13, ?yuv timing? on page 83. table 9-5: input data type selection reg[2ah] bits 3-0 input data type 0000 reserved 0001 rgb 5:6:5 0010 rgb 6:6:6 mode 1 0011 rgb 8:8:8 mode 1 (lsbs will be truncated to 16 bpp or 18 bpp) 0100 reserved 0101 reserved 0110 rgb 6:6:6 mode 2 0111 rgb 8:8:8 mode 2 (lsbs will be truncated to 16 bpp or 18 bpp) 1000 yuv 4:2:2 1001 yuv 4:2:0 1010 ? ? ? 1111 reserved www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 57 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bit 7 reserved the default value for this bit is 0. bit 6 yuv/rgb converter reset this bit performs a software reset of the yuv to rgb converter (yrc). to perform a reset, write a 1 to enter reset, and then write a 0 to return from the reset state. for reads: when this bit = 0, the yrc is not in a reset state. when this bit = 1, the yrc is in a reset state. for writes: writing a 0 to this bit returns the yrc from the reset state. writing a 1 to this bit initiates a software reset of the yrc. bits 5-4 uv fix select bits [1:0] these bits control the uv input to the yuv/rgb converter (yrc). bits 7-6 reserved the default value for these bits is 0. reg[2ch] input yuv/rgb translate mode register 0 default = 00h read/write reserved yuv/rgb converter reset uv fix bits 1-0 n/a 7654 3 2 1 0 table 9-6: uv fix selection reg[2ch] bits 5-4 uv input to the yuv/rgb converter 00 original u data, original v data 01 u data = reg[30h] bits 7-0, original v data 10 original u data, v data = reg[032h] bits 7-0 11 u data = reg[30h] bits 7-0, v data = reg[32h] bits 7-0 reg[2eh] yuv/rgb translate mode register 1 default = 05h read/write reserved yuv input data type select bits 1-0 reserved yuv/rgb transfer mode bits 2-0 7 6 543210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 58 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential bits 5-4 yuv input data type select bits [1:0] these bits specify the data type of the yuv input to the yuv to rgb converter (yrc). bit 3 reserved the default value for this bit is 0. bits 2-0 yuv/rgb transfer mode bits [2:0] these bits specify the yuv/rgb transfer mode. recommended settings are provided for various specifications. table 9-7: yuv data type selection reg[2eh] bits 5-4 yrc input data range 00 0 y 255 -128 u 127 -128 v 127 01 16 y 235 -113 u 112 -113 v 112 10 0 y 255 0 u 255 0 v 255 11 16 y 235 16 u 240 16 v 240 table 9-8: yuv/rgb transfer mode selection reg[2eh] bits 2-0 yuv/rgb specification 000 reserved 001 recommended for itu-r bt.709 010 reserved 011 reserved 100 recommended for itu-r bt.470-6 system m 101 (default) recommended for all other systems in itu-r bt.470-6 (recommended for itu-r bt.601-5) 110 smpte 170m 111 smpte 240m(1987) www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 59 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bits 7-0 u data fix bits [7:0] these bits only have an effect when the uv fix select bits are set to 01 or 11 (reg[2ch] bits 5-4 = 01 or 11). the u data input of the yuv/rgb converter data is fixed to the value of these bits. bits 7-0 v data fix bits [7:0] these bits only have an effect when the uv fix select bits are set to 10 or 11 (reg[2ch] bits 5-4 = 10 or 11). the v data input of yuv/rgb converter data is fixed to the value of these bits. reg[30h] u data fix register default = 00h read/write u data fix bits 7-0 76543210 reg[32h] v data fix register default = 00h read/write v data fix bits 7-0 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 60 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.5 display mode registers bit 7 display blank when this bit = 0, the lcd display pipeline is enabled. when this bit = 1, the lcd display pipeline is disabled and all lcd data outputs are forced to zero (i.e., the screen is blanked). bits 1-0 window swivelview mode select bits [1:0] these bits select different swivelview? orientations: note all windows written to the active display can have independent rotation as the rotation is performed prior to writing to the display buffer. reg[34h] display mode register default = 00h read/write display blank n/a swivelview mode select bits 1-0 7 6 5 4 3 210 table 9-9: swivelview? mode select options reg[34h] bits 1-0 swivelview orientation 00 0 (normal) 01 90 10 180 11 270 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 61 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bit 7 window data type when this bit = 0, the data being written from the host is intended for single buffer only. when this bit = 1, the data being written from the host is intended for double buffer oper- ation. if the input data format is yuv 4:2:0 (reg[2ah] bits 4-0 = 1001), the window data type should not be changed while the yyc is busy (reg[58h] bit 4 = 1). note this bit must be set before the window being written. the window coordinates will be latched internally to be used by the display pipe during display cycles. note this bit setting is necessary for the double-buffer architecture when enabled (bit 6=1) note while double buffering is enabled, the window coordinates should not be modified. reg[36h] special effects register default = 00h read/write window data type double buffer enable n/a window pixel sizing bits 1-0 76 5 4 3 210 table 9-10: window data type/buffer selection reg[36h] bit 7 reg[36h] bit 6 use case 0 0 single buffered window with no double buffering anywhere on the display. 01 use this to write a single buffered window while preventing tearing in a previously defined double buffered window. 10reserved 1 1 use this to write data to be double buffered. www.datasheet.co.kr datasheet pdf - http://www..net/
page 62 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential bit 6 double buffer enable this bit enables the double buffer architecture. when this bit = 0, the double buffer is disabled. when this bit =1, the double buffer is enabled. this feature is only available if the memory size resulting from the display size and color depth will fit within the 1/2 the allowable size for the display buffer. when enabled, this feature is intended for streaming input sources to prevent visual tear- ing when updating the display. note this bit must be set before the window being written. the window coordinates will be latched internally to be used by the display pipe during display cycles. note while double buffering is enabled, the window coordinates should not be modified. note only one window can be double-buffered. all other windows are single buffered. table 9-11: window data type selection reg[36h] bit 7 reg[36h] bit 6 use case 0 0 single buffered window with no double buffering anywhere on the display. 01 use this to write a single buffered window while preventing tearing in a previously defined double buffered window. 10reserved 1 1 use this to write data to be double buffered. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 63 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bits 1-0 window pixel sizing bits [1:0] note these bits must be set before the window being written. the window coordinates will be latched internally to be used by the display pipe during display cycles. note only 1 active window can be pixel doubled. the pixel doubling design uses horizontal and vertical averaging for smooth doubling. note the sizing is performed with respect to the top left corner figure 9-1: sizing example note to turn off pixel doubling for a currently pixel doubled window, either: 1. overwrite any part of the pixel doubled window with a new window. 2. write a new pixel doubled window. table 9-12: window pixel sizing reg[36h] bits 1-0 result 00 no resizing 01 pixel doubling 10 pixel halving 11 reserved original window pixel doubled window pixel halved window display www.datasheet.co.kr datasheet pdf - http://www..net/
page 64 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.6 window settings reg[3ah] bits 1-0 reg[38h] bits 7-0 window x start position bits [9:0] these bits determine the x start position of the window in relation to the top left corner of the displayed image. even in a rotated orientation, the top left corner is still relative to the displayed image. note when pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. reg[3eh] bits 1-0 reg[3ch] bits 7-0 window y start position bits [9:0] these bits determine the y start position of the window in relation to the top left corner of the displayed image. even in a rotated orientation, the top left corner is still relative to the displayed image. note when pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. reg[38h] window x start position register 0 default = 00h read/write window x start position bits 7-0 76543210 reg[3ah] window x start position register 1 default = 00h read/write n/a window x start position bits 9-8 7 6 5 4 3 210 reg[3ch] window y start position register 0 default = 00h read/write window y start position bits 7-0 76543210 reg[3eh] window y start position register 1 default = 00h read/write n/a window y start position bits 9-8 7 6 5 4 3 210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 65 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential reg[42h] bits 1-0 reg[40h] bits 7-0 window x end position bits [9:0] these bits determine the x end position of the window in relation to the top left corner of the displayed image. even in a rotated orientation, the top left corner is still relative to the displayed image. note when pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. reg[46h] bits 1-0 reg[44h] bits 7-0 window y end position bits [9:0] these bits determine the y end position of the window in relation to the top left corner of the displayed image. even in a rotated orientation, the top left corner is still relative to the displayed image. note when pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. reg[40h] window x end position register 0 default = 00h read/write window x end position bits 7-0 76543210 reg[42h] window x end position register 1 default = 00h read/write n/a window x end position bits 9-8 7 6 5 4 3 210 reg[44h] window y end position register 0 default = 00h read/write window y end position bits 7-0 76543210 reg[46h] window y end position register 1 default = 00h read/write n/a window y end position bits 9-8 7 6 5 4 3 210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 66 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.7 memory access reg[48h] bits 7-0 memory data port bits [7:0] these specify the lsb for the data word reg[49h] bits 7-0 memory data port bits [15:8] these bits specify the msb of the data word. note if cnf1=0 (8-bit interface), reg[49h] is not used. the data read back from memory will be byte swapped (i.e. if 12 34 56 78 is written to memory, data read back will be 34 12 78 56). note burst data writes are supported through this register. register auto-increment is auto- matically disabled once reaching this address. all writes to this register will auto-incre- ment the internal memory address only. note panel dimension registers must be set before writing any window data. note upon writing the last pixel in the defined window, this register will automatically point back to the first pixel in the window. therefore there is no need to re-initialize the point- ers. reg[48h] memory data port register 0 default = xxh read/write memory data port bits [7:0] 76543210 reg[49h] memory data port register 1 default = xxh read/write memory data port bits [15:8] 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 67 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential reg[4eh] bits 3-0 reg[4ch] bits 7-0 reg[4ah] bits 7-0 memory read address bits [19:0] this register is only used for individual memory location reads. individual memory location writes are not supported. after a completed memory access, this register is incremented automatically. to perform memory reads: ? perform a register address write to point to this register ? followed by 3 data writes to set-up the memory address ? read the memory data port (reg[48h - 49h]) note all write data uses the memory data port and the window coordinates. note for intel 80, 16-bit interface, the least significant bit is not used (data is fetched on word boundaries). for intel 80, 8-bit interface, the least significant bit is used (data is fetched on byte boundaries) reg[4ah] memory read address register 0 default = 00h read/write memory address bits 7-0 76543210 reg[4ch] memory read address register 1 default = 00h read/write memory address bits 15-8 76543210 reg[4eh] memory read address register 2 default = 00h read/write n/a memory address bit 19-16 7 6 5 43210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 68 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.8 gamma correction registers note gamma correction is implemented as a look-up table. rgb input data (if the input is yuv, it will be converted to rgb first) is used to look-up the values from the pro- grammed tables. the gamma lut?s are placed on the display read path and the 18-bit (6 msb?s from each channel) output goes to the lcd interface. note the gamma correction tables should not be accessed during display period as this will result in visual anomalies. all updates to the lut?s should be performed during non- display period or when the lut?s are disabled and not in use. bits 2-1 look-up table access mode bits [1:0] bit 0 gamma correction enable when this bit = 0, gamma correction is disabled and the input data will bypass the gamma correction look-up table. in this case, data stored as 16 bpp will automatically be con- verted to 18 bpp by copying the red and blue msb to create new lsb?s. this will be per- formed on the display read therefore not requiring any additional memory. when this bit = 1, gamma correction is enabled and the input data will go through the gamma correction look-up table. note the gamma correction tables should not be accessed during display period as this will result in visual anomalies. all updates to the lut?s should be performed during non- display period or when the lut?s are disabled and not in use. reg[50h] gamma correction enable register default = 00h read/write n/a look-up table access mode bits 1-0 gamma correction enable 7 6 5 4 3210 table 9-13: look-up table access mode reg[50h] bits 2-1 description 00 writing will be done to all red, green, & blue tables. reading will be done from red table. 01 reading and writing will be done to red table. 10 reading and writing will be done to green table. 11 reading and writing will be done to blue table. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 69 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bits 5-0 gamma correction table index bits [5:0] these bits will specify the index of the gamma correction look-up table which subsequent read/write will start at. bits 7-0 gamma correction table data bits [7:0] when writing to gamma correction table data register, the index to the internal table will be automatically incremented. for continuous update to the table, the gamma correction table index register needs only to be written once. the index will incremented by 1 for every write to gamma correction table data register. note although bits 7 and 6 are programmed to the lut, they are ignored in the final output from the lut. note all 64 positions of each lut must be written when using auto-increment writes.in the 5:6:5 case, the first 32 positions of the red and blue lut?s will be used. reg[52h] gamma correction table index register default = 00h read/write n/a gamma correction table index bits 5-0 7 6543210 reg[54h] gamma correction table data register default = xxh read/write gamma correction table data bits 5-0 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 70 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.9 miscellaneous registers bit 7 pwrsve input pin function when this bit = 0, the pwrsve pin is or?d with bit 1 (setting either to 1 will enable sleep mode) when this bit = 1, the pwrsve pin is or?d with bit 0 (setting either to 1 will enable standby mode) bit 1 sleep mode enable/disable when this bit = 0, sleep mode is disabled (normal operation) when this bit = 1, sleep mode is enabled. sleep mode disables all internal blocks including the pll. when sleep mode is disabled (low), the pll requires approximately 10msec lock time before any memory access should be attempted. the pll lock bit, reg[04] bit 7, can be read to verify when the pll becomes stable. bit 0 standby mode enable/disable when this bit = 0, standby mode is disabled (normal operation) when this bit = 1, standby mode is enabled standby mode disables all internal blocks except the pll. using this mode, the chip can be accessed immediately when standby is disabled. note standby mode can also be enabled/disabled using the pwrsve input pin. bit 7 vertical non-display period status this is a read-only status bit. when this bit = 0, the lcd panel output is in a vertical non-display period. when this bit = 1, the lcd panel output is in a vertical display period. note vndp is defined as time between the last pixel on the last line of one frame to the first pixel on the first line of the next frame. reg[56h] power save register default = 00h read/write pwrsve input pin function n/a sleep mode enable/disable standby mode enable/disable 7 6 5 4 3 21 0 reg[58h] non-display period control / status register default = 00h read/write vertical non- display period status (ro) horizontal non- display period status (ro) vs or?d with hs status (ro) yyc last line n/a te output pin enable te output pin function select bits 1-0 7654 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 71 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bit 6 horizontal non-display period status this is a read only status bit when this bit = 0, the lcd panel output is in a horizontal non-display period when this bit = 1, the lcd panel output is in a horizontal display period note hndp is defined as the time between the last pixel in line n to the first pixel in line n+1. bit 5 vdp or?d with hdp status this bit is a read only status bit. when this bit = 0, the lcd panel output is in either the horizontal or vertical non-dis- play period. when this bit = 1, the lcd panel output is in a display period. bit 4 yyc last line if the input data type is yuv 4:2:0, this bit will go high 5 mclk?s after the intel 80 inter- face has finished writing the last pixel of the current window. this bit will go low once the yyc is idle. at this point, a new window can be written. when doing back-to-back window writes with a different dimension or format, and the first window is yuv 4:2:0, before starting to write the second window, make sure this bit is low. note it can take up to five sysclks from the rising edge of we# of the last byte/word of a frame before this bit is set. bit 2 te output pin enable when this bit = 0, the te output pin is disabled when this bit = 1, the te output pin is enabled. bits 1-0 te output pin function select bits [1:0] table 9-14: te output pin function select reg[58h] bits 1-0 te output pin function 00 reserved 01 horizontal non-display period 10 vertical non-display period 11 hs or?d with vs www.datasheet.co.kr datasheet pdf - http://www..net/
page 72 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 9.3.10 general purpose io pins registers bits 7-0 gpio[7:0] configuration when this bit = 0 (normal operation), the associated gpio is configured as an input pin. when this bit = 1, the associated gpio is configured as an output pin. note when configured as an input or an output, the associated gpio can also be configured to produce an interrupt (gpio_int) based on selectable interrupt trigger conditions (see reg[5e], [60]) bits 7-0 gpio[7:0] status when the associated gpio is configured as an output, writing a 1 to this bit drives it high and writing a 0 to this bit drives it low. when the associated gpio is configured as an input, a read from this bit returns the raw status. note when configured as an output, the gpio_int pin can still be toggled by writing the ap- propriate value to this register if enabled by reg[5e],[60]. bits 7-0 gpio[7:0] positive edge interrupt trigger setting these bits = 1, will enable the associated interrupt. this bit determines whether the associated gpio interrupt is triggered on the positive edge (when the gpiox pin changes from 0 to 1). when this bit = 0, the associated gpio interrupt (gpio_int) is disabled. when this bit = 1, the associated gpio interrupt (gpio_int) is triggered on the positive edge. once triggered, the gpio_int pin will toggle from 0 to 1. the gpio_int pins is cleared (non-active state (0)) by clearing the associated gpio interrupt status bit (reg[62]) reg[5ah] general purpose io pins configuration register 0 default =00h read/write gpio7 configuration gpio6 configuration gpio5 configuration gpio4 configuration gpio3 configuration gpio2 configuration gpio1 configuration gpio0 configuration 76543210 reg[5ch] general purpose io pins status/control register 0 default = 00h read/write gpio7 status gpio6 status gpio5 status gpio4 status gpio3 status gpio2 status gpio1 status gpio0 status 76543210 reg[5eh] gpio positive edge interrupt trigger register default = 00h read/write gpio7 positive edge interrupt trigger gpio6 positive edge interrupt trigger gpio5 positive edge interrupt trigger gpio4 positive edge interrupt trigger gpio3 positive edge interrupt trigger gpio2 positive edge interrupt trigger gpio1 positive edge interrupt trigger gpio0 positive edge interrupt trigger 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 73 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential bits 7-0 gpio[7:0] negative edge interrupt trigger setting these bits = 1, will enable the associated interrupt. this bit determines whether the associated gpio interrupt is triggered on the negative edge (when the gpiox pin changes from 1 to 0). when this bit = 0, the associated gpiox interrupt (gpio_int) is disabled. when this bit = 1, the associated gpiox interrupt (gpio_int) is triggered on the negative edge. once triggered, the gpio_int pin will toggle from 0 to 1. the gpio_int pins is cleared (non-active state (0)) by clearing the associated gpio interrupt status bit (reg[62]) bits 7-0 gpio[7:0] interrupt status if configured to generate an interrupt (gpio_int), this status bit will show which gpio generated the interrupt. to clear this status bit, you must perform two writes to it: first write = 1, the second write = 0. note the gpio_int pin will also toggle back to 0 upon clearing the status. however, if the original interrupt condition still exists on the gpio input pin, the gpio_int will imme- diately set again. bits 7-0 gpio[7:0] pull-down control all gpio pins have internal pull-down resistors. these bits individually control the state of the pull-down resistors. when the bit = 0, the pull-down resistor for the associated gpio pin is inactive. when the bit = 1, the pull-down resistor for the associated gpio pin is active. reg[60h] gpio negative edge interrupt trigger register default = 00h read/write gpio7 negative edge interrupt trigger gpio6 negative edge interrupt trigger gpio5 negative edge interrupt trigger gpio4 negative edge interrupt trigger gpio3 negative edge interrupt trigger gpio2 negative edge interrupt trigger gpio1 negative edge interrupt trigger gpio0 negative edge interrupt trigger 76543210 reg[62h] gpio interrupt status register default = 00h read/write gpio7 interrupt status gpio6 interrupt status gpio5 interrupt status gpio4 interrupt status gpio3 interrupt status gpio2 interrupt status gpio1 interrupt status gpio0 interrupt status 76543210 reg[64h] gpio pull down control register 0 default = ffh read/write gpio7 pull-down control gpio6 pull-down control gpio5 pull-down control gpio4 pull-down control gpio3 pull-down control gpio2 pull-down control gpio1 pull-down control gpio0 pull-down control 76543210 www.datasheet.co.kr datasheet pdf - http://www..net/
page 74 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 10 frame rate calculation the following formula is used to calculate the display frame rate. where: f pclk = pclk frequency (hz) ht = horizontal total = horizontal display width + horizontal non-display period vt = vertical total = vertical display height + vertical non-display period note for definitions of panel timing parameters, see section 7.4, ?display interface? on page 35. framerate f pclk ht () vt () -------------------------------- = www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 75 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 11 intel 80, 8-bit interface color formats 11.1 16 bpp mode (r 5-bit, g 6-bit, b 5-bit), 65,536 colors figure 11-1: 16 bpp mode (r 5-bit, g 6-bit, b 5-bit), 65,536 colors note: the data order is as follows, msb = md7, lsb = md0 and picture data is msb = bit 5, lsb = bit 0 for green data and msb = bit 4, lsb = bit 0 for red and blue data. cs# d/c# wr# rd# md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r1, bit 4 r1, bit 3 r1, bit 2 r1, bit 1 r1, bit 0 g1, bit 5 g1, bit 4 g1, bit 3 g1, bit 2 g1, bit 1 g1, bit 0 b1, bit 4 b1, bit 3 b1, bit 2 b1, bit 1 b1, bit 0 r2, bit 4 r2, bit 3 r2, bit 2 r2, bit 1 r2, bit 0 g2, bit 5 g2, bit 4 g2, bit 3 g2, bit 2 g2, bit 1 g2, bit 0 b2, bit 4 b2, bit 3 b2, bit 2 b2, bit 1 b2, bit 0 r1, bit 1 pixel pixel n www.datasheet.co.kr datasheet pdf - http://www..net/
page 76 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 11.2 18 bpp (r 6-bit, g 6-bit, b 6-bit), 262,144 colors figure 11-2: 18 bpp (r 6-bit, g 6-bit, b 6-bit), 262,144 colors note: the data order is as follows, msb = md7, lsb = md0 and picture data is msb = bit 5, lsb = bit 0. cs# d/c# wrx rd# md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r1, bit 4 r1, bit 3 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 b1, bit 4 b1, bit 2 b1, bit 0 b1, bit 1 b1, bit 5 b1, bit 3 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 pixel n + 1 pixel n www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 77 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 11.3 24 bpp (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors figure 11-3: 24 bpp (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors note: the data order is as follows, msb = md7, lsb = md0 and picture data is msb = bit 7, lsb = bit 0. cs# d/c# wr# rd# md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r1, bit 4 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 r1, bit 7 r1, bit 6 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 g1, bit 7 g1, bit 6 b1, bit 4 b1, bit 2 b1, bit 0 b1, bit 1 b1, bit 5 b1, bit 3 b1, bit 7 b1, bit 6 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 r2, bit 7 r2, bit 6 pixel n + 1 pixel n www.datasheet.co.kr datasheet pdf - http://www..net/
page 78 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 12 intel 80, 16-bit interface color formats 12.1 16 bpp (r 5-bit, g 6-bit, b 5-bit), 65,536 colors figure 12-1: 16 bpp (r 5-bit, g 6-bit, b 5-bit), 65,536 colors note: the data order is as follows, msb = md15, lsb = md0 and picture data is msb = bit 5, lsb = bit 0 for green data and msb = bit 4, lsb = bit 0 for red and blue data. pixel n + 2 pixel n pixel n + 1 cs# d/c# wr# rd# md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r1, bit 4 r1, bit 3 r1, bit 2 r1, bit 0 r1, bit 1 r2, bit 4 r2, bit 3 r2, bit 2 r2, bit 0 r2, bit 1 r3, bit 4 r3, bit 3 r3, bit 2 r3, bit 0 r3, bit 1 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 g2, bit 4 g2, bit 2 g2, bit 0 g2, bit 1 g2, bit 5 g2, bit 3 g3, bit 4 g3, bit 2 g3, bit 0 g3, bit 1 g3, bit 5 g3, bit 3 b1, bit 4 b1, bit 3 b1, bit 2 b1, bit 0 b1, bit 1 b2, bit 4 b2, bit 3 b2, bit 2 b2, bit 0 b2, bit 1 b3, bit 4 b3, bit 3 b3, bit 2 b3, bit 0 b3, bit 1 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 79 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 12.2 18 bpp mode 1 (r 6-bit, g 6-bit, b 6-bit), 262,144 colors figure 12-2: 18 bpp mode 1(r 6-bit, g 6-bit, b 6-bit), 262,144 colors note: the data order is as follows, msb = md15, lsb = md0 and picture data is msb = bit 5, lsb = bit 0. pixel n pixel n + 1 cs# d/c# wr# rd# md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r1, bit 4 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 g2, bit 4 g2, bit 2 g2, bit 0 g2, bit 1 g2, bit 5 g2, bit 3 b1, bit 4 b1, bit 2 b1, bit 0 b1, bit 1 b1, bit 5 b1, bit 3 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 b2, bit 4 b2, bit 2 b2, bit 0 b2, bit 1 b2, bit 5 b2, bit 3 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 www.datasheet.co.kr datasheet pdf - http://www..net/
page 80 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 12.3 18 bpp mode 2 (r 6-bit, g 6-bit, b 6-bit), 262,144 colors figure 12-3: 18 bpp mode 2 (r 6-bit, g 6-bit, b 6-bit), 262,144 colors note: the data order is as follows, msb = md15, lsb = md0 and picture data is msb = bit 5, lsb = bit 0. pixel n pixel n + 1 cs# d/c# wr# rd# md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 b2, bit 4 b2, bit 2 b2, bit 0 b2, bit 1 b2, bit 5 b2, bit 3 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 r1, bit 4 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 81 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 12.4 24 bpp mode 1 (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors figure 12-4: 24 bpp mode 1(r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors note: the data order is as follows, msb = md15, lsb = md0 and picture data is msb = bit 7, lsb = bit 0. cs# d/c# wr# rd# md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r1, bit 4 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 r1, bit 7 r1, bit 6 g2, bit 4 g2, bit 2 g2, bit 0 g2, bit 1 g2, bit 5 g2, bit 3 g2, bit 7 g2, bit 6 b1, bit 4 b1, bit 2 b1, bit 0 b1, bit 1 b1, bit 5 b1, bit 3 b1, bit 7 b1, bit 6 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 g1, bit 7 g1, bit 6 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 r2, bit 7 r2, bit 6 b2, bit 4 b2, bit 2 b2, bit 0 b2, bit 1 b2, bit 5 b2, bit 3 b2, bit 7 b2, bit 6 pixel n pixel n + 1 www.datasheet.co.kr datasheet pdf - http://www..net/
page 82 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 12.5 24 bpp mode 2 (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors figure 12-5: 24 bpp mode 2 (r 8-bit, g 8-bit, b 8-bit), 16,777,216 colors note: the data order is as follows, msb = md15, lsb = md0 and picture data is msb = bit 7, lsb = bit 0. cs# d/c# wr# rd# md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 g1, bit 4 g1, bit 2 g1, bit 0 g1, bit 1 g1, bit 5 g1, bit 3 g1, bit 7 g1, bit 6 r1, bit 4 r1, bit 2 r1, bit 0 r1, bit 1 r1, bit 5 r1, bit 3 r1, bit 7 r1, bit 6 b1, bit 4 b1, bit 2 b1, bit 0 b1, bit 1 b1, bit 5 b1, bit 3 b1, bit 7 b1, bit 6 r2, bit 4 r2, bit 2 r2, bit 0 r2, bit 1 r2, bit 5 r2, bit 3 r2, bit 7 r2, bit 6 pixel n pixel n + 1 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 83 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 13 yuv timing format definition ? the number of pixels per line is always even ?the yc b c r colorspace is defined in itu-r bt601.4 ? yuv 4:2:2 format u 11 y 11 v 11 y 12 u 13 y 13 v 13 y 14 ... ? yuv 4:2:0 format odd line: uy 11 y 12 ... even line: vy 21 y 22 ... note when a window is setup for yuv data, the data must always alternate between odd and even lines, starting with an odd line. figure 13-1: yuv format definition odd line even line yuv 4:2:2 y13 y14 y24 u/v y23 yuv 4:2:0 y11 y12 y22 u/v y21 odd line even line (must start with this line) u11 y12 u13 y14 y11 y13 v11 v13 u21 y22 u23 y24 y21 y23 v21 v23 www.datasheet.co.kr datasheet pdf - http://www..net/
page 84 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 13.1 yuv 4:2:2 with intel 80, 8-bit interface figure 13-2: yuv 4:2:2 with intel 80, 8-bit interface 13.2 yuv 4:2:0 odd line with intel 80, 8-bit interface figure 13-3: yuv 4:2:0 odd line with intel 80, 8-bit interface d / c # w r # b i t 0 c s # r d # m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 u y 1 4 v y 1 3 u y 1 2 v y 1 1 ( 1 1 , 1 2 ) ( 1 1 , 1 2 ) ( 1 3 , 1 4 ) ( 1 3 , 1 4 ) r e s e t # d / c # w r # b i t 0 c s # r d # b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 u ( 1 1 , 1 2 , 2 1 , 2 2 ) y 1 5 u ( 1 5 , 1 6 , 2 5 , 2 6 ) y 1 4 y 1 3 u ( 1 3 , 1 4 , 2 3 , 2 4 ) y 1 2 y 1 1 m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 r e s e t # www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 85 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 13.3 yuv 4:2:0 even line with intel 80, 8-bit interface figure 13-4: yuv 4:2:0 even line with intel 80, 8-bit interface d / c # w r # b i t 0 c s # r d # b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 v ( 1 1 , 1 2 , 2 1 , 2 2 ) y 2 5 v ( 1 5 , 1 6 , 2 5 , 2 6 ) y 2 4 y 2 3 v ( 1 3 , 1 4 , 2 3 , 2 4 ) y 2 2 y 2 1 m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 r e s e t # www.datasheet.co.kr datasheet pdf - http://www..net/
page 86 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 13.4 yuv 4:2:2 with intel 80, 16-bit interface figure 13-5: yuv 4:2:2 with intel 80, 16-bit interface b i t 8 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 u 1 1 v 1 7 u 1 7 v 1 5 u 1 5 v 1 3 u 1 3 v 1 1 b i t 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 y 1 1 y 1 8 y 1 7 y 1 6 y 1 5 y 1 4 y 1 3 y 1 2 d / c # w r # c s # r e s e t # r d # m d 1 5 m d 1 4 m d 1 3 m d 1 2 m d 1 1 m d 1 0 m d 9 m d 8 m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 87 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 13.5 yuv 4:2:0 odd line with intel 80, 16-bit interface figure 13-6: yuv 4:2:0 odd line with intel 80, 16-bit interface b i t 8 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 u ( 1 1 , 1 2 , 2 1 , 2 2 ) y 1 7 y 1 6 u ( 1 5 , 1 6 , 2 5 , 2 6 ) y 1 3 y 1 2 b i t 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 y 1 1 y 1 8 u ( 1 7 , 1 8 , 2 7 , 2 8 ) y 1 5 y 1 4 u ( 1 3 , 1 4 , 2 3 , 2 4 ) ) d / c # w r # c s # r e s e t # r d # m d 1 5 m d 1 4 m d 1 3 m d 1 2 m d 1 1 m d 1 0 m d 9 m d 8 m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 www.datasheet.co.kr datasheet pdf - http://www..net/
page 88 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 13.6 yuv 4:2:0 even line with intel 80, 16-bit interface figure 13-7: yuv 4:2:0 even line with intel 80, 16-bit interface b i t 8 b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9 v ( 1 1 , 1 2 , 2 1 , 2 2 ) y 2 7 y 2 6 v ( 1 5 , 1 6 , 2 5 , 2 6 ) y 2 3 y 2 2 b i t 0 b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 y 2 1 y 2 8 v ( 1 7 , 1 8 , 2 7 , 2 8 ) y 2 5 y 2 4 v ( 1 3 , 1 4 , 2 3 , 2 4 ) d / c # w r # c s # r e s e t # r d # m d 1 5 m d 1 4 m d 1 3 m d 1 2 m d 1 1 m d 1 0 m d 9 m d 8 m d 7 m d 6 m d 5 m d 4 m d 3 m d 2 m d 1 m d 0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 89 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 14 gamma correction look -up table architecture the following figures are intended to show the display data output path only. the following diagram shows the architecture for 18 bpp using lut. figure 14-1: look-up table architecture red look-up table 64x8 00 0000 00 0001 6-bit red data 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 00 0000 00 0001 6-bit green data 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 00 0000 00 0001 6-bit blue data 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 green look-up table 64x8 00 01 02 03 04 05 06 07 38 39 3a 3b 3c 3d 3e 3f blue look-up table 64x8 00 01 02 03 04 05 06 07 38 39 3a 3b 3c 3d 3e 3f 00 01 02 03 04 05 06 07 38 39 3a 3b 3c 3d 3e 3f note: only the 6 lsb?s from each table are used to construct an 18-bit pixel. 6-bit red data from display buffer 6-bit green data from display buffer 6-bit blue data from display buffer www.datasheet.co.kr datasheet pdf - http://www..net/
page 90 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 14.1 gamma correction example programming ? disable the lut?s or ensure you are in a non-display period when accessing to avoid visual anomalies. ? write register ?address? for gamma correction enable register. ? write data to set lut access mode. ? write data to set lut index to ?x? (auto-increment is already enabled therefore the lut index register address does not have to be written). ? write data to gamma correction data register (data value for index ?x?). ? write data to gamma correction data register (data value for index ?x+1?). ? continue until complete (64 positions). even in the case of 5:6:5, all 64 positions of each rgb lut must be programmed when using the auto-increment method. ? enable gamma correction. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 91 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 15 display data format table 15-1: 36-bit data format (non-swapped) cycle count 1 2 3 ... n vd35 r 1 5 r 3 5 r 5 5 ... r n+1 5 vd34 r 1 4 r 3 4 r 5 4 ... r n+1 4 vd33 r 1 3 r 3 3 r 5 3 ... r n+1 3 vd32 r 1 2 r 3 2 r 5 2 ... r n+1 2 vd31 r 1 1 r 3 1 r 5 1 ... r n+1 1 vd30 r 1 0 r 3 0 r 5 0 ... r n+1 0 vd29 g 1 5 g 3 5 g 5 5 ... g n+1 5 vd28 g 1 4 g 3 4 g 5 4 ... g n+1 4 vd27 g 1 3 g 3 3 g 5 3 ... g n+1 3 vd26 g 1 2 g 3 2 g 5 2 ... g n+1 2 vd25 g 1 1 g 3 1 g 5 1 ... g n+1 1 vd24 g 1 0 g 3 0 g 5 0 ... g n+1 0 vd23 b 1 5 b 3 5 b 5 5 ... b n+1 5 vd22 b 1 4 b 3 4 b 5 4 ... b n+1 4 vd21 b 1 3 b 3 3 b 5 3 ... b n+1 3 vd20 b 1 2 b 3 2 b 5 2 ... b n+1 2 vd19 b 1 1 b 3 1 b 5 1 ... b n+1 1 vd18 b 1 0 b 3 0 b 5 0 ... b n+1 0 vd17 r 0 5 r 2 5 r 4 5 ... r n 5 vd16 r 0 4 r 2 4 r 4 4 ... r n 4 vd15 r 0 3 r 2 3 r 4 3 ... r n 3 vd14 r 0 2 r 2 2 r 4 2 ... r n 2 vd13 r 0 1 r 2 1 r 4 1 ... r n 1 vd12 r 0 0 r 2 0 r 4 0 ... r n 0 vd11 g 0 5 g 2 5 g 4 5 ... g n 5 vd10 g 0 4 g 2 4 g 4 4 ... g n 4 vd9 g 0 3 g 2 3 g 4 3 ... g n 3 vd8 g 0 2 g 2 2 g 4 2 ... g n 2 vd7 g 0 1 g 2 1 g 4 1 ... g n 1 vd6 g 0 0 g 2 0 g 4 0 ... g n 0 vd5 b 0 5 b 2 5 b 4 5 ... b n 5 vd4 b 0 4 b 2 4 b 4 4 ... b n 4 vd3 b 0 3 b 2 3 b 4 3 ... b n 3 vd2 b 0 2 b 2 2 b 4 2 ... b n 2 vd1 b 0 1 b 2 1 b 4 1 ... b n 1 vd0 b 0 0 b 2 0 b 4 0 ... b n 0 www.datasheet.co.kr datasheet pdf - http://www..net/
page 92 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential table 15-2: 36-bit data format (swapped) cycle count 1 2 3 ... n vd35 b 0 0 b 2 0 b 4 0 ... b n 0 vd34 b 0 1 b 2 1 b 4 1 ... b n 1 vd33 b 0 2 b 2 2 b 4 2 ... b n 2 vd32 b 0 3 b 2 3 b 4 3 ... b n 3 vd31 b 0 4 b 2 4 b 4 4 ... b n 4 vd30 b 0 5 b 2 5 b 4 5 ... b n 5 vd29 g 0 0 g 2 0 g 4 0 ... g n 0 vd28 g 0 1 g 2 1 g 4 1 ... g n 1 vd27 g 0 2 g 2 2 g 4 2 ... g n 2 vd26 g 0 3 g 2 3 g 4 3 ... g n 3 vd25 g 0 4 g 2 4 g 4 4 ... g n 4 vd24 g 0 5 g 2 5 g 4 5 ... g n 5 vd23 r 0 0 r 2 0 r 4 0 ... r n 0 vd22 r 0 1 r 2 1 r 4 1 ... r n 1 vd21 r 0 2 r 2 2 r 4 2 ... r n 2 vd20 r 0 3 r 2 3 r 4 3 ... r n 3 vd19 r 0 4 r 2 4 r 4 4 ... r n 4 vd18 r 0 5 r 2 5 r 4 5 ... r n 5 vd17 b 1 0 b 3 0 b 5 0 ... b n+1 0 vd16 b 1 1 b 3 1 b 5 1 ... b n+1 1 vd15 b 1 2 b 3 2 b 5 2 ... b n+1 2 vd14 b 1 3 b 3 3 b 5 3 ... b n+1 3 vd13 b 1 4 b 3 4 b 5 4 ... b n+1 4 vd12 b 1 5 b 3 5 b 5 5 ... b n+1 5 vd11 g 1 0 g 3 0 g 5 0 ... g n+1 0 vd10 g 1 1 g 3 1 g 5 1 ... g n+1 1 vd9 g 1 2 g 3 2 g 5 2 ... g n+1 2 vd8 g 1 3 g 3 3 g 5 3 ... g n+1 3 vd7 g 1 4 g 3 4 g 5 4 ... g n+1 4 vd6 g 1 5 g 3 5 g 5 5 ... g n+1 5 vd5 r 1 0 r 3 0 r 5 0 ... r n+1 0 vd4 r 1 1 r 3 1 r 5 1 ... r n+1 1 vd3 r 1 2 r 3 2 r 5 2 ... r n+1 2 vd2 r 1 3 r 3 3 r 5 3 ... r n+1 3 vd1 r 1 4 r 3 4 r 5 4 ... r n+1 4 vd0 r 1 5 r 3 5 r 5 5 ... r n+1 5 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 93 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential table 15-3: 18-bit data format (non-swapped) cycle count 1 2 3 ... n vd[35:18] driven low vd17 r 0 5 r 1 5 r 2 5 ... r n 5 vd16 r 0 4 r 1 4 r 2 4 ... r n 4 vd15 r 0 3 r 1 3 r 2 3 ... r n 3 vd14 r 0 2 r 1 2 r 2 2 ... r n 2 vd13 r 0 1 r 1 1 r 2 1 ... r n 1 vd12 r 0 0 r 1 0 r 2 0 ... r n 0 vd11 g 0 5 g 1 5 g 2 5 ... g n 5 vd10 g 0 4 g 1 4 g 2 4 ... g n 4 vd9 g 0 3 g 1 3 g 2 3 ... g n 3 vd8 g 0 2 g 1 2 g 2 2 ... g n 2 vd7 g 0 1 g 1 1 g 2 1 ... g n 1 vd6 g 0 0 g 1 0 g 2 0 ... g n 0 vd5 b 0 5 b 1 5 b 2 5 ... b n 5 vd4 b 0 4 b 1 4 b 2 4 ... b n 4 vd3 b 0 3 b 1 3 b 2 3 ... b n 3 vd2 b 0 2 b 1 2 b 2 2 ... b n 2 vd1 b 0 1 b 1 1 b 2 1 ... b n 1 vd0 b 0 0 b 1 0 b 2 0 ... b n 0 www.datasheet.co.kr datasheet pdf - http://www..net/
page 94 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential table 15-4: 18-bit data format (swapped) cycle count 1 2 3 ... n vd[35:18] driven low vd17 b 0 0 b 1 0 b 2 0 ... b n 0 vd16 b 0 1 b 1 1 b 2 1 ... b n 1 vd15 b 0 2 b 1 2 b 2 2 ... b n 2 vd14 b 0 3 b 1 3 b 2 3 ... b n 3 vd13 b 0 4 b 1 4 b 2 4 ... b n 4 vd12 b 0 5 b 1 5 b 2 5 ... b n 5 vd11 g 0 0 g 1 0 g 2 0 ... g n 0 vd10 g 0 1 g 1 1 g 2 1 ... g n 1 vd9 g 0 2 g 1 2 g 2 2 ... g n 2 vd8 g 0 3 g 1 3 g 2 3 ... g n 3 vd7 g 0 4 g 1 4 g 2 4 ... g n 4 vd6 g 0 5 g 1 5 g 2 5 ... g n 5 vd5 r 0 0 r 1 0 r 2 0 ... r n 0 vd4 r 0 1 r 1 1 r 2 1 ... r n 1 vd3 r 0 2 r 1 2 r 2 2 ... r n 2 vd2 r 0 3 r 1 3 r 2 3 ... r n 3 vd1 r 0 4 r 1 4 r 2 4 ... r n 4 vd0 r 0 5 r 1 5 r 2 5 ... r n 5 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 95 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 16 swivelview? 16.1 concept most computer displays are refreshed in landscape orientation ? from left to right and top to bottom. computer images are stored in the same manner. swivelview? is designed to rotate the displayed image on an lcd by 90 , 180 , or 270 in a counter-clockwise direction . the rotation is done in hardware and is transparent to the user for all display buffer writes. by processing the rotation in hardware, swivelview? offers a performance advantage over software rotation of the displayed image. the actual address translation is performed during the host write and is therefore stored in memory as rotated. because of where the rotation logic is, each window written to the S1D13742 can be independently rotated with respect to each other. 16.2 90 swivelview? the following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. the application image is written to the S1D13742 in the following sense: a?b?c?d. the display is refreshed in the following sense: b-d-a-c. figure 16-1: relationship between the screen image and the image refreshed in 90 swivelview. 16.2.1 register programming there is no special programming requirements other than simply enabling the rotation itself. all start addresses and line offset?s are automatically calculated by hardware. image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 swivelview window display start address image refreshed by the S1D13742 (panel origin) physical memory start address www.datasheet.co.kr datasheet pdf - http://www..net/
page 96 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 16.3 180 swivelview? the following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. the application image is written to the S1D13742 in the following sense: a?b?c?d. the display is refreshed in the following sense: d-c-b-a. figure 16-2: relationship between the screen image and the image refreshed in 180 swivelview. 16.3.1 register programming there is no special programming requirements other than simply enabling the rotation itself. all start addresses and line offset?s are automatically calculated by hardware. image seen by programmer = image in display buffer 480 swivelview window 480 320 ab cd 320 image refreshed by the S1D13742 swivelview window ab cd display start address (panel origin) physical memory start address www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 97 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 16.4 270 swivelview? the following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. the application image is written to the S1D13742 in the following sense: a?b?c?d. the display is refreshed in the following sense: c-a-d-b. figure 16-3: relationship between the screen image and the image refreshed in 270 swivelview. 16.4.1 register programming there is no special programming requirements other than simply enabling the rotation itself. all start addresses and line offset?s are automatically calculated by hardware. image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 swivelview window image refreshed by the S1D13742 physical memory display start address (panel origin) start address www.datasheet.co.kr datasheet pdf - http://www..net/
page 98 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 17 host interface 17.1 using the intel 80 interface accessing the S1D13742 through the intel 80 interface is a multiple step process. all registers and memory are accessed through register space. note all register accesses, except the memory data port, are 8-bit only. if the host in- terface is 16-bits wide, the lsb?s (md[7:0]) are used for all registers except the memory data port. the memory data port (reg[48h, 49h]) is handled as 8-bit if cnf1 = 0 (reg[49h] not used) or 16-bit if cnf1 =1. first, perform a single ?address write? to setup the register address. next a ?data read/write? is performed that specifies the data to be stored or read from the registers or memory specified in the ?address write? cycle. subsequent data read/writes without a address write to change the register address, will automatically ?auto? increment the register address or the internal memory address if accessing the memory data port. to write display data to a window aperture, simply set-up the window coordinates followed by the burst data writes to the memory data port to fill the window. in this sequence, the internal memory addressing is automatic (see examples). the memory data port is located directly following the window coordinates to minimize the number of address writes. to read display data, perform an address write to the memory address port (3 bytes) and then read data from the memory data port. sequential reads will auto-increment the internal memory address 17.1.1 register write procedure 1. perform address write to setup register address bits 7-0. 2. perform data write to update the register. 3. additional data writes are supported. in this case, the register addresses will be auto- incremented. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 99 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential figure 17-1: register write example sequence 17.1.2 register read procedure 1. perform address write to setup register address bits 7-0. 2. perform data read to get the register value. 3. additional data reads are supported. in this case, the register addresses will be auto-in- cremented. figure 17-2: register read example sequence d/c# cs# we# rd# md[7:0] address bits 7-0 write 1 data write 3 data write 4 data write 2 d/c# cs# rd# md[7:0] we# md[7:0] write read address bits 7-0 write 1 data read 3 data read 4 data read 2 www.datasheet.co.kr datasheet pdf - http://www..net/
page 100 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 17.1.3 new window aperture write procedure the S1D13742 has a special procedure to minimize set-up accesses when bursting window data. 1. the panel dimension registers must be set before writing any window data. 2. perform an address write to point to the first window register (window x start po- sition). 3. perform eight ?data? writes to the next eight, 8-bit registers (this will set-up all the window coordinates. note in this case the register addresses will be auto-incremented until you reach the memory data port register 4. perform burst data writes to fill the window (the register address will already be point- ing at the memory data port) the memory data port register is located in the 9th register address after the window x start position. every write to the memory data port will auto-increment the internal memory address only. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 101 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential figure 17-3: sequential memory write example sequence d/c# cs# we# rd# md[7:0] window x start register address window x start data window x start data window y start data window y start data window x end data window x end data window y end data window y end data display data www.datasheet.co.kr datasheet pdf - http://www..net/
page 102 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 17.1.4 opening multiple windows 1. repeat steps above (new window aperture write procedure) with new window coor- dinates for each new window. 2. non-pixel doubled windows can overlap with the last one being written considered the top. update window using existing window coordinates: 1. perform an address write to point to the memory data port 2. perform burst data writes to fill the window. note in this case the previous coordinates of the window aperture will be used. every write to the memory data port will auto-increment the internal memory address only. 17.1.5 individual memory location reads note this function is for test purposes only and serves no practical use in a system. 1. set the memory data format to 16bpp. 2. write the physical address of the memory location to read from, to the memory read address registers (for a 16bit bus, the lsb of this address is ignored). 3. perform a read from the memory data port register. 4. continuous reads from the memory data port register will cause the address in the memory read address registers to increment, thereby supporting burst reads. note to access the 2 msb?s for each 18-bit value, you must know the physical address as they are stored at different locations as compared to the lower 16-bits. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 103 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 18 double buffer description 18.1 double buffer controller double buffering is provided to prevent tearing of streaming video data. all static (non- video) image data will always be written to the upper half (buffer 1) of the frame buffer. when video is being input, the first frame will be written to the lower half (buffer 2) of the double buffer. the second frame will be written to buffer 1. while video data is being input, the static part of the image going to the lcd will still always come from buffer 1. the source of the video window will come from either buffer 1 or buffer 2, depending on which one was the last to be completely updated. the switching of the buffer read/write pointers can only occur once per frame, at the beginning of the vertical non-display period. the pointers will only switch if: a video frame had completed being updated within the last output frame period, and no new video frame is currently being written. because of this, each time the user finishes writing a frame of video data, they should wait until the next vertical non-display period before writing the next frame. this can be accomplished by using the te pin or by polling the vertical display period status (reg[58h] bit 7). alternatively, if the user can guarantee that the maximum input video frame rate is 1/2 the lcd frame rate and that the burst length for writing a video frame is less than one lcd frame period, then no checking for the vertical non-display period is required. if attention is not paid to allowing the pointers to switch, then frames may be dropped. figure 18-1: switching of buffer pointers to use the double buffer feature: ? set the special effects register reg[36h] bits 7-6 to 11. ? setup the window position registers reg[38h] - reg[46h]. ? write the video data to the memory data port reg[48h] - reg[49h]. vertical non-display period input video frame burst switch buffer pointers don?t switch buffer pointers since a frame is currently being written. read buffer pointer write buffer pointer since a frame completed being updated in the last lcd frame period switch buffer pointers since a frame completed being updated in the last lcd frame period switch buffer pointers since a frame completed being updated in the last lcd frame period www.datasheet.co.kr datasheet pdf - http://www..net/
page 104 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential it is also possible to update a static window while double buffering is enabled, even in the middle of a video stream. to do this: ? write the last pixel of the current frame of video data. ? set the special effects register reg[36h] bits 7-6 to 01. ? setup the window position registers reg[38h] - reg[46h]. ? write the static data to the memory data port reg[48h] - reg[49h]. this allows a static image to be written at any time, while still preventing the double buffered window from tearing. once the static window has been written, the user can go back to writing the streaming video data by following the steps described above for using the double buffer feature. figure 18-2: double buffer example background image background image background image background image buffer 1 buffer 1 buffer 1 buffer 1 buffer 2 buffer 2 buffer 2 buffer 2 output output input input time 1: the main/background image is in buffer 1. buffer 2 is empty. the data output to the lcd comes entirely from buffer 1. time 2: the main/background image is in buffer 1. buffer 2 is written with video data. the data output to the lcd comes entirely from buffer 1. time 3: the main/background image is in buffer 1, but part of this data is destructively overwritten by the second frame of video data. the static image data from buffer 1 is sent to the lcd, but the video window comes from buffer 2. output pip time 4: a static pip is destructively written output input into buffer 1. since the most recently updated video frame is in buffer 1, the entire image output to the lcd comes from buffer 1. there may be tearing in the pip window, but the video window will not tear. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 105 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential there are some limitations to double buffering: ? consider the case where there is a video stream being input and the user wants to place a static pip over all or some part of the video window. the user can write the pip, but when the video stream is continued, it will destructively overwrite the pip, so that it will appear as though the pip is under the video window. ? consider the case where there is a video stream which stops after the last frame of video is sent. the final frame of video will continue to be displayed on the lcd. assume that this last frame is stored in buffer 2. now, if the user disables double buffering, the buffer read pointer will immediately reset to buffer 1. this means that the 2nd to last frame will now be displayed instead of the last frame. ? the user must either wait for a vertical non-display period between writing frames of video data, or guarantee that their maximum input frame rate is 1/2 the lcd frame rate and that the length of time it takes to burst write a frame of video data is less than one lcd frame period. ? only one window can be double buffered at a time. www.datasheet.co.kr datasheet pdf - http://www..net/
page 106 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 19 interfacing the S1D13742 and a tft panel this section describes the hardware and software environment required to interface the S1D13742 mobile graphics engine and a 352x416 or 800x480 tft panel. the designs described in this section are presented only as examples of how such interfaces might be implemented. 19.1 overview the S1D13742 was designed to directly support the sanyo lc13015 and requires no additional hardware and minimal programming. the S1D13742 register settings and electrical interface is described below. 19.1.1 electrical interface table 19-1: pin mapping S1D13742 pin name S1D13742 pin number lcd13015 pin name hs d9 hs vs d10 vs pclk d11 pclk de c11 de vd[17:0] j8,j9,j10,j11,k4,k5,k6,k 7,k8,k9,k10,l3,l4,l5,l6, l7,l8,l9 r5,r4,r3,r2,r1,r0,g5,g 4,g3,g2,g1,g0,b5,b4,b3, b2,b1,b0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 107 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 19.1.2 S1D13742 register settings for 352x416 tft panel note the registers listed below are only those associated with panel specific timing issues all other registers are not shown here. note when a window is setup for yuv data, the data must always alternate between odd and even lines, starting with an odd line. table 19-2: example register settings for 352x416 tft panel register value comment all default come out of reset - all registers set to default values reg[56h] 02h enter sleep mode (or use pwrsve pin) reg[04h] 12h set pll m-divider. clki = 19.2mhz, pll input clock = clki/19 = 1.01mhz. reg[06h] f8h reg[08h] 80h reg[0ah] 28h reg[0ch] 00h reg[0eh] 2fh ll = 48, resulting sysclk = ll x pll input clock = 48mhz reg[12h] 19h set pclk divide, pclk = 12.1mhz set sysclk source = pll reg[14h] 0h no panel data swap, 18-bit panel reg[16h] 2ch hdp = 352 pixels reg[18h] 5ah hndp = 90 pixels reg[1ah] a0h vdp = 416 lines reg[1ch] 01h reg[1eh] 06h vndp = 6 lines reg[20h] 14h hs pulse width = 20 pixels reg[22h] 2dh hs start position = 45 pixels reg[24h] 02h vs width = 2 lines reg[26h] 01h vs start position (vfp) = 1 line reg[28h] 80h pclk polarity: data output on falling edge reg[2ah] 01h set memory to 16 bpp, set input data mode to rgb 5:6:5 reg[56h] 00h disable sleep mode reg[04h] bit 7 ? wait for pll to lock - poll reg[04h] bit 7 reg[38h] 00h window x start position = 0 reg[3ah] 00h reg[3ch] 00h window y start position = 0 reg[3eh] 00h www.datasheet.co.kr datasheet pdf - http://www..net/
page 108 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential note the above values are intended as examples. this example assumes that clki = 19.2mhz and that the pll is used to generate sysclk. actual settings can vary and still remain within the lcd panel timing requirements. reg[40h] 5fh window x end position = 351 reg[42h] 01h reg[44h] 9fh window y end position = 415 reg[46h] 01h reg[48h] write the image data to the memory data port, reg[48h] and reg[49h]. the image will immediately begin to appear on the lcd. reg[49h] table 19-2: example register settings for 352x416 tft panel (continued) register value comment www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 109 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 19.1.3 S1D13742 register settings for 800x480 tft panel note the registers listed below are only those associated with panel specific timing issues all other registers are not shown here. note when a window is setup for yuv data, the data must always alternate between odd and even lines, starting with an odd line. table 19-3: example register settings for 800x480 tft panel register value comment all default come out of reset - all registers set to default values reg[56h] 02h enter sleep mode (or use pwrsve pin) reg[04h] 0bh set pll m-divider. clki = 12mhz, pll input clock = clki/12 = 1.0mhz. reg[06h] f8h reg[08h] 80h reg[0ah] 28h reg[0ch] 00h reg[0eh] 2dh ll = 45, resulting sysclk = ll x pll input clock = 45mhz reg[12h] 09h set pclk divide, pclk = 22.5mhz set sysclk source = pll reg[14h] 0h no panel data swap, 18-bit panel reg[16h] 64h hdp = 800 pixels reg[18h] 14h hndp = 20 pixels reg[1ah] e0h vdp = 480 lines reg[1ch] 01h reg[1eh] 06h vndp = 6 lines reg[20h] 14h hs pulse width = 20 pixels reg[22h] 2dh hs start position = 45 pixels reg[24h] 02h vs width = 2 lines reg[26h] 01h vs start position (vfp) = 1 line reg[28h] 80h pclk polarity: data output on falling edge reg[2ah] 01h set memory to 16 bpp, set input data mode to rgb 5:6:5 reg[56h] 00h disable sleep mode reg[04h] bit 7 ? wait for pll to lock - poll reg[04h] bit 7 reg[38h] 00h window x start position = 0 reg[3ah] 00h reg[3ch] 00h window y start position = 0 reg[3eh] 00h www.datasheet.co.kr datasheet pdf - http://www..net/
page 110 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential note the above values are intended as examples. this example assumes that clki = 12mhz and that the pll is used to generate sysclk. actual settings can vary and still remain within the lcd panel timing requirements. reg[40h] 1fh window x end position = 799 reg[42h] 03h reg[44h] dfh window y end position = 479 reg[46h] 01h reg[48h] write the image data to the memory data port, reg[48h] and reg[49h]. the image will immediately begin to appear on the lcd. reg[49h] table 19-3: example register settings for 800x480 tft panel (continued) register value comment www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 111 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 19.2 host bus timing figure 19-1: intel 80 input a.c. characteristics d/c# cs# we# md[15:0] rd# md[15:0] t ast t aht t cs t csf t csf t wc t wrl t wrh t dst t dht t rcs t rc t rdl t rdh t aht t odh t rat note: the d/c# input pin is used to distinguish between address and data. note: the register address will auto-increment in word increments for all register access except the gamma correction table data register and memory data port. writes to the gamma correction table data register and memory data port will not increment the register address to support burst data writes to the gamma correction table and to memory. t ddt write read ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd ?iovdd www.datasheet.co.kr datasheet pdf - http://www..net/
page 112 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 19.2.1 host bus timing for 352x416 tft panel sysclk = 48mhz, pclk = 12mhz, clki = 12mhz 1. t wrh min = long enough to satisfy t wc 2. t rdh min = long enough to satisfy t rc table 19-4: intel 80 input a.c. characteristics (352x416 panel timings) signal symbol parameter min max unit description d/c# t ast address setup time 1.4 ? nsec t aht address hold time 0.3 ? nsec cs# t cs chip select setup time (write) 0.6 + twrl ? nsec t rcs chip select setup time (read) 1.3 + trdl ? nsec t csf chip select wait time 9.2 ? nsec we# t wc write cycle (rising edge to next rising edge) 42.6 ? nsec t wrh pulse high duration note 1 ? t wrl pulse low duration 0.1 ? nsec rd# t rc read cycle for registers 42.6 ? nsec read cycle for memory 122.1 + trdh ? nsec read cycle for lut 108.1 + trdh ? nsec t rdh pulse high duration note 2 ? t rdl pulse low duration for registers 10.2 ? nsec pulse low duration for memory 122.1 ? nsec pulse low duration for lut 108.1 ? nsec md[15:0] t dst data setup time 0.3 ? nsec for maximum cl=30pf for minimum cl=8pf t dht data hold time 6.4 ? nsec t rat (see note) read falling edge to data valid for registers ? 12.2 nsec read falling edge to data valid for memory ? 122.1 nsec read falling edge to data valid for lut ? 108.1 nsec t odh (see note) read hold time 10.7 32.1 nsec t ddt (see note) read falling edge to data driven 3.0 12.3 nsec www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 113 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 19.2.2 host bus timing for 800x480 tft panel sysclk = 59 mhz, pclk = 19.67 mhz, clki = 12mhz 1. t wrh min = long enough to satisfy t wc 2. t rdh min = long enough to satisfy t rc table 19-5: intel 80 input a.c. characteristics (800x480 panel timings) signal symbol parameter min max unit description d/c# t ast address setup time 1.4 ? nsec t aht address hold time 0.3 ? nsec cs# t cs chip select setup time (write) 0.6 + twrl ? nsec t rcs chip select setup time (read) 1.3 + trdl ? nsec t csf chip select wait time 9.2 ? nsec we# t wc write cycle (rising edge to next rising edge) 34.8 ? nsec t wrh pulse high duration note 1 ? t wrl pulse low duration 0.1 ? nsec rd# t rc read cycle for registers 34.8 ? nsec read cycle for memory 102.7 + trdh ? nsec read cycle for lut 92.5 + trdh ? nsec t rdh pulse high duration note 2 ? t rdl pulse low duration for registers 10.2 ? nsec pulse low duration for memory 102.7 ? nsec pulse low duration for lut 92.5 ? nsec md[15:0] t dst data setup time 0.3 ? nsec for maximum cl=30pf for minimum cl=8pf t dht data hold time 6.4 ? nsec t rat (see note) read falling edge to data valid for registers ? 12.2 nsec read falling edge to data valid for memory ? 102.7 nsec read falling edge to data valid for lut ? 92.5 nsec t odh (see note) read hold time 10.7 32.1 nsec t ddt (see note) read falling edge to data driven 3.0 12.3 nsec www.datasheet.co.kr datasheet pdf - http://www..net/
page 114 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 19.3 panel timing figure 19-2: 18/36-bit tft a.c. timing t3 t5 hs t1 t4 vs de pclk 320 t2 hs 2 1 t13 t10 t11 t14 t15 t16 t7 t8 t9 t12 vd[17:0] note: 2 pixels/clock mode t6 invalid invalid n+1 3-4 1-2 vd[35:0] invalid invalid note: 1 pixel/clock mode pclk t13 t10 t11 t14 t9 t12 reg[28h] b7=1 reg[28h] b7=0 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 115 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 19.3.1 panel timing for 352x416 panel 1. ts = pixel clock period = 83.3 ns (12mhz pclk) 19.3.2 panel timing for 800x480 panel 1. ts = pixel clock period = 50.84 (19.67 pclk) table 19-6: 18/36-bit tft a.c. timing (352x416 panel timing) symbol parameter min typ max units t1 vs cycle time 15.54 ? ms t2 vs pulse width low 73.67 ? us t3 vs falling edge to hs falling edge phase difference 0 ? 36.75 us t4 hs cycle time 36.83 ? us t5 hs pulse width low 1.67 ? us t6 hs falling edge to de active 3.75 ? us t7 de pulse width 29.3 ? us t8 de falling edge to hs falling edge 3.75 ? us t9 pclk period 83.3 ? ? ns t10 pclk pulse width low 41.7 ? ? ns t11 pclk pulse width high 41.7 ? ? ns t12 hs setup to pclk falling edge 41.7 ? ? ns t13 de to pclk rising edge setup time 41.7 ? ? ns t14 de hold from pclk rising edge 41.7 ? ? ns t15 data setup to pclk rising edge 41.7 ? ? ns t16 data hold from pclk rising edge 41.7 ? ? ns table 19-3 18/36-bit tft a.c. timing (800x480 panel timings) symbol parameter min typ max units t1 vs cycle time 20.34 ? ms t2 vs pulse width low 83.4 ? us t3 vs falling edge to hs falling edge phase difference 0 ? 41.63 us t4 hs cycle time 41.68 ? us t5 hs pulse width low 1.02 ? us t6 hs falling edge to de active 966 ? ns t7 de pulse width 40.67 ? us t8 de falling edge to hs falling edge 50.84 ? ns t9 pclk period 50.84 ? ? ns t10 pclk pulse width low 25.42 ? ? ns t11 pclk pulse width high 25.42 ? ? ns t12 hs setup to pclk falling edge 25.42 ? ? ns t13 de to pclk rising edge setup time 25.42 ? ? ns t14 de hold from pclk rising edge 25.42 ? ? ns t15 data setup to pclk rising edge 25.42 ? ? ns t16 data hold from pclk rising edge 25.42 ? ? ns www.datasheet.co.kr datasheet pdf - http://www..net/
page 116 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 19.4 example play.exe scripts the following example scripts are written for the play.exe program. the script demo.txt will initialize the S1D13742, then display horizontal bars at different rotations, and then display a pip+ window. demo.txt verbose cmd:off out:on set:off halt 0 '============================================================================== ' _demo_.txt - play script for 13742 to demonstrate various features. ' ' this demonstration code is written in the play.exe script language so that ' various steps can be easily observed. some steps such as the initialization ' and the memory fills use play intrinsic commands. these operation of these ' commands are easily determined. '============================================================================== ' initialize the registers to the default state by ' running the register list generated by 13742cfg '---------------------------------------------------------- init ' set the window to the full screen and clear the display '---------------------------------------------------------- setwin.txt f win 0 ' rotate 0 '---------------------------------------------------------- print "color bars at swivelview 0\n" x 34 0 drawbarsa.txt pause.txt ' rotate 90 ' note: there is a bug with the fill window command in ' play which causes the 90 and 270 degree fills ' to be filled incorrectly. this will be corrected. '---------------------------------------------------------- print "color bars at swivelview 90\n" x 34 1 drawbarsb.txt pause.txt ' rotate 180 '---------------------------------------------------------- print "color bars at swivelview 180\n" x 34 2 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 117 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential drawbarsa.txt pause.txt ' rotate 270 ' note: there is a bug with the fill window command in ' play which causes the 90 and 270 degree fills ' to be filled incorrectly. this will be corrected. '---------------------------------------------------------- print "color bars at swivelview 270\n" x 34 3 drawbarsb.txt pause.txt ' pip '---------------------------------------------------------- print "draw color bars in a pip (small window)\n" x 34 0 setwin.txt f win 0 drawbarsa.txt drawpip.txt 50 50 100 128 pause.txt section end www.datasheet.co.kr datasheet pdf - http://www..net/
page 118 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential drawbarsa.txt verbose cmd:off out:on set:off '============================================================================== ' drawbars.txt - play script for the 13742 ' ' this script draws eight equally sized horizontal ' bars on the display. '============================================================================== set $height ((reg[1c] << 8) + (reg[1a])) set $lines ($height / 8) set $startx 0 set $starty 0 set $endx width set $endy $lines set $color 0 set $bars 8 section loop setwin.txt $startx $starty $endx $endy f win $color set $starty ($starty + $lines) set $endy ($endy + $lines) set $color ($color + 0821) set $bars ($bars - 1) if $bars!=0 then goto loop www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 119 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential drawbarsb.txt verbose cmd:off out:on set:off '============================================================================== ' drawbarsb.txt - play script for the 13742 ' ' this script draws horizontal bars in swivelview 90 and swivelview 270 ' display modes. '============================================================================== set $height (reg[16] * 8) set $lines ($height / 8) set $startx 0 set $starty 0 set $endx height set $endy $lines set $color 0 set $bars 8 section loop setwin.txt $startx $starty $endx $endy f win $color set $starty ($starty + $lines) set $endy ($endy + $lines) set $color ($color + 0821) set $bars ($bars - 1) if $bars!=0 then goto loop www.datasheet.co.kr datasheet pdf - http://www..net/
page 120 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential drawpip.txt verbose cmd:off out:on set:off '============================================================================== ' drawpip.txt - play script for the 13742 ' ' this script draws eight equally sized horizontal bars on the display. '============================================================================== set $startx arg[1].nt set $starty arg[2].nt set $width arg[3].nt set $height arg[4].nt set $lines ($height / 8) set $color 0 set $bars 8 section loop setwin.txt $startx $starty $width $lines f win $color set $starty ($starty + $lines) set $color ($color + 0821) set $bars ($bars - 1) if $bars!=0 then goto loop pause.txt verbose cmd:off out:on set:off halt 0 print "paused . . . press any key to continue\n" input line www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 121 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential setwin.txt verbose cmd:off out:on set:off '------------------------------------------------------------------------------ ' setwin.txt - play script for the 13742 ' ' this script is functionally identical to the play command 'win'. call this ' script to set the 13742 window co-ordinates as specified by the arguments. ' ' syntax: setwin x y w h ' where: x - left edge window x position ' y - top edge window y position ' w - window width ' h - window height ' ' example: setwin 0 0 100 100 ' sets the window to start at 0,0 and end at 100, 100 ' ' setwin ' sets the window size to the size of the display ' ' win sx:0 sy:0 ex:width ey:height '------------------------------------------------------------------------------ ' set the default window values to the display size. set $sx 0 set $sy 0 set $ex (width - 1) set $ey (height - 1) ' use non-default values only if all four arguments are given if (argn!=5) then goto setwindow set $sx arg[1].n set $sy arg[2].n set $ex (arg[1].n + arg[3].n - 1) set $ey (arg[2].n + arg[4].n - 1) section setwindow ' change the register window settings x 38 $sx x 3a ($sx >> 8) x 3c $sy x 3e ($sy >> 8) x 40 $ex x 42 ($ex >> 8) x 44 $ey x 46 ($ey >> 8) www.datasheet.co.kr datasheet pdf - http://www..net/
page 122 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 19.5 references 19.5.1 documents ? sanyo electric co., ltd. display company , lc13015 low temperature p-si tft-lcd specification , document number lc13015-040302 ? epson research and development, inc., S1D13742 hardware functional specification , document number x63a-a-001-xx. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 123 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 20 pll power supply considerations the pll circuit is an analog circuit which is very sensitive to noise on the input clock waveform or the power supply. noise on the clock or the supplied power may cause the operation of the pll circuit to become unstable or increase the jitter. due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the pll be isolated from those of other power supplies. filtering should also be used to keep the power as clean as possible. the following are guidelines which, if followed, will result in cleaner power to the pll, this will result in a cleaner and more stable clock. even a partial implementation of these guidelines will give results. 20.1 guidelines for pll power layout the pll circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. noise on the clock or the supplied power may cause the operation of the pll circuit to become unstable or increase the jitter. due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the pll be isolated from those of other power supplies. filtering should also be used to keep the power as clean as possible. the following are guidelines which, if followed, will result in cleaner power to the pll, resulting in a cleaner and more stable clock. even a partial implementation of these guide- lines will give results. figure 20-1: pll power layout voltage regulator S1D13742 pllvdd pllvss optional, but recommended notes: l1 l2 c2 c3 c1 to digital vss plane to digital iovdd plane pll power traces must split from the digital traces very close to the regulator ? pllvdd and pllvss traces should be as short as possible ? pllvdd and pllvss must be separated from the digital supply ? digital power and ground to l1 and l2 should be short parallel traces on the same side of the board to reduce any loop area that can induce noise typical values: l1, l2 c1 c2 c3 isolation bead ~10uf bypass 1nf bypass .1uf bypass actual values may be different and subject to validation www.datasheet.co.kr datasheet pdf - http://www..net/
page 124 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential ? place the ferrite beads (l1 and l2) parallel to each other with minimal clearance between them. both bypass caps (c2 and c3) should be as close as possible to the inductors. the traces from c3 to the power planes should be short parallel traces on the same side of the board with just the normal small clearance between them. any signifi- cant loop area here will induce noise. if there is a voltage regulator on the board, try to run these power traces directly to the regulator instead of dropping to the power planes (still follow above rules about parallel traces). ? the analog ground point where bypass cap (c2) connects to the ground isolation inductor (l2) becomes the analog ground central point for a ground star topology. none of the components connect directly to the analog ground pin of the mge (pllvss) except for a single short trace from c2 to the pllvss pin. the ground side of the large bypass capacitor (c1) should also have a direct connection to the star point. ? the same star topology rules used for analog ground apply to the analog power connec- tion where l2 connects to c2. ? all of the trace lengths should be as short as possible. ? if possible, have all the pll traces on the same outside layer of the board. the only exception is c1, which can be put on the other side of the board if necessary. c1 does not have to be as close to the analog ground and power star points as the other compo- nents. ? if possible, include a partial plane under the pll area only (area under pll components and traces). the solid analog plane should be grounded to the c2 (bypass) pad. this plane won?t help if it is too large. it is strictly an electrostatic shield against coupling from other layers? signals in the same board area. if such an analog plane is not possible, try to have the layer below the pll components be a digital power plane instead of a signal layer. ? if possible, keep other board signals from running right next to pll pin vias on any layer. ? wherever possible use thick traces, especially with the analog ground and power star connections to either side of c2. try to make them as wide as the component pads ? thin traces are more inductive. it is likely that manufacturing rules will prohibit routing the ground and power star connec- tions as suggested. for instance, four wide traces converging on a single pad could have reflow problems during assembly because of the thermal effect of all the copper traces around the capacitor pad. one solution might be to have only a single trace connecting to the pad and then have all the other traces connecting to this wide trace a minimum distance away from the pad. another solution might be to have the traces connect to the pad, but with thermal relief around the pad to break up the copper connection. ultimately the board must also be manufacturable, so best effort is acceptable. www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 125 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 21 mechanical data figure 21-1: S1D13742 fcbga 121-pin package 0.65 0.75 0.3 0.05 0.65 units = mm 0.75 1234567891011 a b c d e f g h j k l top view side view bottom view a1 corner a1 corner 8.0 0.20 die size die size 8.0 0.20 1.0 max. 0.28 0.05 www.datasheet.co.kr datasheet pdf - http://www..net/
page 126 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential figure 21-2: S1D13742 qfp20 144-pin package index units = mm 73 108 37 72 36 1 144 109 d h d h e e eb a max a 1 a 2 c l symbol dimension in millimeters min nom max e?20? d?20? h e ?22? h d ?22? a max ??1.7 a 1 ?0.1? a 2 ?1.4? e?0.5? b 0.17 ? 0.27 c0.09?0.2 0 ? 10 l0.3?0.75 l 1 ?1? y??0.08 l 1 y s www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 127 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential figure 21-3: S1D13742 fcbga 121-pin package marking units = mm ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) c0.74 2.28 3.18 cc aaa ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) y x? x y? package center line package center line a = 0.3 b = 0.4 c = 0.6 d = 0.1 e = 0.2 number of row and column not fixed index mark 0.8 2.2 2.13 0.8 3.03 ddd ddddd b ee b b b bbbb + " 1 / " % item no. notes logo specified (1) device name (2) ~ (5) die revision code (6) package type (7) c: fcbga process and package revision code (8) [blank] (9) ~ (10) control code (11) ~ (19) year of manufacture (12) ~ (13) last two numbers of a.d. month of manufacture (14) ~ (15) 1-9: jan - sep x: oct, y: nov, z: dec w/f lot no. (16) ~ (19) japan (20) ~ (24) www.datasheet.co.kr datasheet pdf - http://www..net/
page 128 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential figure 21-4: S1D13742 qfp 144-pin package marking units = mm 8.0 y x? x y? package center line package center line a = 0.8 b = 0.25 c = 1.0 d = 0.5 item no. notes logo specified (1) epson japan (2) ~ (6) device name (7) ~ (19) S1D13742f01a2 control code (20) ~ (28) year of manufacture (21) ~ (22) last two numbers of a.d. week of manufacture (23) ~ (24) calendar week of the year w/f lot no. (25) ~ (28) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) 2.0 aaaaa 0.3 bbbb 1.2 a 1.5 aaaaa bbbb aaaa bbbb a 1.2 cc ccc c c cc cc c bbbbbbbbbbbb dd pin 1 xx? y y? www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 129 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential 22 references the following documents contain additional information related to the S1D13742. document numbers are listed in parenthesis after the document name. all documents can be found at the epson research and development website at www.erd.epson.com . ? S1D13742 product brief (x63a-c-001-xx) ? s5u13742p00c100 evaluation board user manual (x63a-g-002-xx) www.datasheet.co.kr datasheet pdf - http://www..net/
page 130 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential 23 sales and technical support 23.1 ordering information to order the S1D13742 mobile graphics engine, contact the epson sales representative in your area. america epson electronics america, inc. headquarters 2580 orchard parkway san jose , ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 www.datasheet.co.kr datasheet pdf - http://www..net/
epson research and development page 131 vancouver design center hardware functional specification S1D13742 issue date: 2007/09/18 x63a-a-001-06 revision 6.01 - epson confidential change record x63a-a-001-06 revision 6.01 - issued: 2007/09/18 ? all changes from the last revision of the spec are highlighted in red ? section 5.1, for the intel 80 data pin mapping tables, swapped the md[15:8] descrip- tions for cnf1=0, b00 should be ?internal resistors? and b01 should be ?hi-z? ? section 7.3.1 ~ 7.3.2, added note and clarified the usage of md[15:8] pins in the host timing figures and tables ? section 17.1.3, updated the x/y start/end data order in the sequential memory write example sequence figure and moved it to section 17.1.3 ? section 22, added references ? section 23, added sales and technical support addresses x63a-a-001-06 revision 6.0 (issued 2007/05/29) ? all changes from the last revision of the spec are highlighted in red ? section 14 gamma correction look-up table architecture - correct typos in figure 14 - 1; change data from display buffers to 6 bit, change the multiplexers to 64 positions from 256 ? section 19.1.3 S1D13742 register settings for 800x480 tft panel - correct typo in table 19-3, change the reg[04h] value to 0bh x63a-a-001-05 revision 5.02 (issued 2006/08/23) ? all changes from the last revision of the spec are highlighted in red ? globally add qfp20 144-pin package information ? section 5.3 lcd interface data pins - correct typos in table, change hi-z to driven low ? section 6.3 electrical characteristics - add table 6-5 electrical characteristics for iovdd or piovdd = 3.3v 0.3v ? section 7.2 reset# timing - add clki signal to figure ? section 7.3.1 intel 80 interface timing - 1.8 volt - rewrite section for 1.8 volts ? section 7.3.2 intel 80 interface timing - 3.3 volt - add this section ? reg[2ah] bits 4-0 - add note ?rgb 6:6:6 mode 2 and rgb 8:8:8 mode 2...? x63a-a-001-05 revision 5.01 (issued 2006/04/28) ? updated epson tagline ? all changes from the last revision of the spec are highlighted in red ? section 4.2.1 intel 80 host interface - for md[15:0] rewrite the note in pin description, for gpio_int add reference to general purpose io pins registers to pin description. ? section 4.2.2 lcd interface - for vd[35:0] rewrite both notes in pin description www.datasheet.co.kr datasheet pdf - http://www..net/
page 132 epson research and development vancouver design center S1D13742 hardware functional specification x63a-a-001-06 issue date: 2007/09/18 revision 6.01 - epson confidential ? section 4.2.4 miscellaneous - for gpio[7:0] rewrite pin description, for pwrsve rewrite pin description for no pull-down resistor ? section 4.2.4, change scanen pin description io voltage from ?vss? to ?iovdd? ? section 7.2 reset# timing - add this section ? section 17.1.2 and 17.1.5, for the host interface section changed the references in the figures from ?d[15:0]? to ?md[15:0]? ? fixed typo in change record, document numbers should be listed as ?x63...? instead of ?x59...? ? section 6.3 electrical characteristics - in tables 6-3 and 6-4, define the conditions for quiescent current x63a-a-001-04 revision 4.0 (issued 2005/11/29) ? section 7.3.3 18/36-bit tft panel timing - correct typos in figure 7-8 18/36-bit tft a/c timing - change references to reg[2ah] to reg[28h], change t17 reference to falling edge of vs, and in table 7-7 18/36-bit tft a/c timing change pclk edge references to ?active? www.datasheet.co.kr datasheet pdf - http://www..net/

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